hw/lx_rocon_top.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5 use ieee.numeric_std.all;
   6
   7 -- library unisim;
   8 -- use unisim.vcomponents.all;
   9
  10 use work.mbl_pkg.all;
  11 use work.lx_rocon_pkg.all;
  12
  13 -- lx_rocon_top - wires the modules with the outside world
  14
  15 -- ======================================================
  16 --  MASTER CPU EXTERNAL MEMORY BUS
  17 -- ======================================================
  18 --
  19 -- Master cpu memory bus has the following wires:
  20 --
  21 -- - address[15..0]          The address, used to mark chip enable
  22 -- - data_in[31..0]          The data coming to bus
  23 -- - data_out[31..0]         The data coming from bus, multiplexed
  24 -- - bls[3..0]               Write enable for respective bytes
  25
  26 entity lx_rocon_top is
  27         port
  28         (
  29                 -- External
  30                 --clk_cpu     : in std_logic;
  31                 clk_50m     : in std_logic;
  32                 --
  33                 cs0_xc      : in std_logic;
  34                 --
  35                 rd          : in std_logic;
  36                 bls         : in std_logic_vector(3 downto 0);
  37                 address     : in std_logic_vector(15 downto 0);
  38                 data        : inout std_logic_vector(31 downto 0);
  39                 --
  40                 irc0_a      : in std_logic;
  41                 irc0_b      : in std_logic;
  42                 irc0_index  : in std_logic;
  43                 irc0_mark   : in std_logic;
  44                 --
  45                 irc1_a      : in std_logic;
  46                 irc1_b      : in std_logic;
  47                 irc1_index  : in std_logic;
  48                 irc1_mark   : in std_logic;
  49                 --
  50                 irc2_a      : in std_logic;
  51                 irc2_b      : in std_logic;
  52                 irc2_index  : in std_logic;
  53                 irc2_mark   : in std_logic;
  54                 --
  55                 irc3_a      : in std_logic;
  56                 irc3_b      : in std_logic;
  57                 irc3_index  : in std_logic;
  58                 irc3_mark   : in std_logic;
  59                 --
  60                 irc4_a      : in std_logic;
  61                 irc4_b      : in std_logic;
  62                 irc4_index  : in std_logic;
  63                 irc4_mark   : in std_logic;
  64                 --
  65                 irc5_a      : in std_logic;
  66                 irc5_b      : in std_logic;
  67                 irc5_index  : in std_logic;
  68                 irc5_mark   : in std_logic;
  69                 --
  70                 irc6_a      : in std_logic;
  71                 irc6_b      : in std_logic;
  72                 irc6_index  : in std_logic;
  73                 irc6_mark   : in std_logic;
  74                 --
  75                 irc7_a      : in std_logic;
  76                 irc7_b      : in std_logic;
  77                 irc7_index  : in std_logic;
  78                 irc7_mark   : in std_logic;
  79                 --
  80                 init        : in std_logic;
  81                 --
  82                 s1_clk_in   : in std_logic;
  83                 s1_miso     : in std_logic;
  84                 s1_sync_in  : in std_logic;
  85                 --
  86                 s1_clk_out  : out std_logic;
  87                 s1_mosi     : out std_logic;
  88                 s1_sync_out : out std_logic;
  89                 -- signal connected to external JK FF
  90                 event_jk_j  : out std_logic
  91         );
  92 end lx_rocon_top;
  93
  94 architecture Behavioral of lx_rocon_top is
  95
  96         -- Reset signal
  97         signal reset_s                  : std_logic;
  98         signal init_s                   : std_logic;
  99         -- Peripherals on the memory buses
 100         -- Master to Tumbl DMEM / IMEM (Master)
 101         signal tumbl_out_s              : std_logic_vector(31 downto 0);
 102         signal tumbl_ce_s               : std_logic;
 103         -- Measurement (Master)
 104         signal meas_out_s               : std_logic_vector(31 downto 0);
 105         signal meas_ce_s                : std_logic;
 106         -- Master to Tumbl XMEM
 107         signal master_tumbl_xmem_out_s  : std_logic_vector(31 downto 0);
 108         signal master_tumbl_xmem_ce_s   : std_logic;
 109         signal master_tumbl_xmem_lock_s : std_logic;
 110         -- IRC (Tumbl)
 111         signal irc_proc_out_s            : std_logic_vector(31 downto 0);
 112         signal irc_proc_ce_s             : std_logic;
 113         signal irc_proc_next_ce_s        : std_logic;
 114         -- LX Master (Tumbl)
 115         signal lxmaster_out_s           : std_logic_vector(15 downto 0);
 116         signal lxmaster_ce_s            : std_logic;
 117         signal lxmaster_next_ce_s       : std_logic;
 118         -- LX function approximation
 119         signal lxfncapprox_out_s        : std_logic_vector(31 downto 0);
 120         signal lxfncapprox_ce_s         : std_logic;
 121         signal lxfncapprox_next_ce_s    : std_logic;
 122         -- Signals for external bus transmission
 123         signal data_i_s                 : std_logic_vector(31 downto 0);
 124         signal data_o_s                 : std_logic_vector(31 downto 0);
 125         -- Signals for internal transaction
 126         signal last_address_s           : std_logic_vector(15 downto 0);
 127         signal next_last_address_s      : std_logic_vector(15 downto 0);
 128         signal next_address_hold_s      : std_logic;
 129         signal address_hold_s           : std_logic;
 130         signal last_rd_s                : std_logic;
 131         signal next_last_rd_s           : std_logic;
 132         signal last_bls_s               : std_logic_vector(3 downto 0); -- prev bls_f_s (active 1)
 133         signal next_last_bls_s          : std_logic_vector(3 downto 0);
 134
 135         -- Reading logic for Master CPU:
 136         -- Broadcast rd only till ta (transaction acknowledge)
 137         -- is received, then latch the data till the state of
 138         -- rd or address changes
 139         --
 140         -- Data latching is synchronous - it's purpose is to
 141         -- provide stable data for CPU on the bus
 142         signal cs0_xc_f_s          : std_logic;
 143         signal rd_f_s              : std_logic; -- Filtered RD
 144         signal i_rd_s              : std_logic; -- Internal bus RD (active 1)
 145         -- signal next_i_rd_s         : std_logic;
 146         signal last_i_rd_s         : std_logic; -- Delayed RD bus, used for latching
 147         signal next_last_i_rd_s    : std_logic;
 148         signal i_rd_cycle2_s       : std_logic; -- Some internal subsystems provide
 149         signal next_i_rd_cycle2_s  : std_logic; -- data only after 2 cycles
 150         --
 151         signal address_f_s         : std_logic_vector(15 downto 0); -- Filtered address
 152         --
 153         signal data_f_s            : std_logic_vector(31 downto 0); -- Filterred input data
 154         --
 155         signal data_read_s         : std_logic_vector(31 downto 0); -- Latched read data
 156         signal next_data_read_s    : std_logic_vector(31 downto 0);
 157
 158         -- Writing logic:
 159         signal bls_f_s             : std_logic_vector(3 downto 0); -- Filtered BLS (active 1)
 160         signal i_bls_s             : std_logic_vector(3 downto 0); -- Internal BLS (active 1)
 161         signal next_i_bls_s        : std_logic_vector(3 downto 0);
 162         --
 163         signal data_write_s        : std_logic_vector(31 downto 0); -- Data broadcasted to write
 164         signal next_data_write_s   : std_logic_vector(31 downto 0);
 165
 166         -- Tumbl:
 167         signal tumbl_bls_s         : std_logic_vector(3 downto 0);
 168         signal tumbl_address_s     : std_logic_vector(14 downto 0);
 169         signal tumbl_data_i_s      : std_logic_vector(31 downto 0);
 170         --
 171         signal tumbl_xmemb_o_s     : CORE2DMEMB_Type;
 172         signal tumbl_xmemb_i_s     : DMEMB2CORE_Type;
 173         signal tumbl_xmemb_sel_s   : std_logic;
 174         -- Interrupt event sources and processing
 175         signal lxmaster_rx_done_s  : std_logic;
 176         signal lxmaster_rx_done_r  : std_logic;
 177         signal lxmaster_rx_done_last_s : std_logic;
 178         signal lxmaster_rx_done_last_r : std_logic;
 179
 180         -- signal s0   : std_logic;
 181         -- signal s1   : std_logic;
 182         -- signal s2   : std_logic;
 183
 184         -- XST attributes
 185         attribute REGISTER_DUPLICATION : string;
 186         -- attribute REGISTER_DUPLICATION of rd : signal is "NO";
 187         attribute REGISTER_DUPLICATION of rd_f_s : signal is "NO";
 188         -- attribute REGISTER_DUPLICATION of bls : signal is "NO";
 189         attribute REGISTER_DUPLICATION of bls_f_s : signal is "NO";
 190         -- attribute REGISTER_DUPLICATION of address : signal is "NO";
 191         attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
 192         -- attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
 193
 194 begin
 195
 196 -- Tumbl coprocessor
 197 memory_bus_tumbl: bus_tumbl
 198         port map
 199         (
 200                 clk_i          => clk_50m,
 201                 reset_i        => reset_s,
 202                 ce_i           => tumbl_ce_s,
 203                 bls_i          => i_bls_s,
 204                 address_i      => address_f_s(11 downto 0),
 205                 data_i         => data_i_s,
 206                 data_o         => tumbl_out_s,
 207                 --
 208                 xmemb_o        => tumbl_xmemb_o_s,
 209                 xmemb_i        => tumbl_xmemb_i_s,
 210                 xmemb_sel_o    => tumbl_xmemb_sel_s
 211         );
 212
 213 -- Measurement
 214 memory_bus_measurement: bus_measurement
 215         port map
 216         (
 217                 clk_i     => clk_50m,
 218                 reset_i   => reset_s,
 219                 ce_i      => meas_ce_s,
 220                 address_i => address_f_s(1 downto 0),
 221                 bls_i     => i_bls_s,
 222                 data_i    => data_i_s,
 223                 data_o    => meas_out_s
 224         );
 225
 226
 227 -- LX Master
 228 memory_bus_lxmaster: bus_lxmaster
 229         port map
 230         (
 231                 reset_i        => reset_s,
 232                 --
 233                 clk_i          => clk_50m,
 234                 address_i      => tumbl_address_s(10 downto 0),
 235                 next_ce_i      => lxmaster_next_ce_s,
 236                 data_i         => tumbl_data_i_s(15 downto 0),
 237                 data_o         => lxmaster_out_s,
 238                 bls_i          => tumbl_bls_s(1 downto 0),
 239                 --
 240                 rx_done_o      => lxmaster_rx_done_s,
 241                 --
 242                 clock_i        => s1_clk_in,
 243                 miso_i         => s1_miso,
 244                 sync_i         => s1_sync_in,
 245                 --
 246                 clock_o        => s1_clk_out,
 247                 mosi_o         => s1_mosi,
 248                 sync_o         => s1_sync_out
 249                 --
 250                 -- clock_i        => s0,
 251                 -- miso_i         => s1,
 252                 -- sync_i         => not s2,
 253                 --
 254                 -- clock_o        => s0,
 255                 -- mosi_o         => s1,
 256                 -- sync_o         => s2
 257         );
 258
 259         -- s1_clk_out      <= s0;
 260         -- s1_mosi         <= s1;
 261         -- s1_sync_out     <= s2;
 262
 263
 264 function_approx: component lx_fncapprox
 265         port map
 266         (
 267                 reset_i      => reset_s,
 268                 clk_i        => clk_50m,
 269                 -- Data bus
 270                 address_i      => tumbl_address_s(4 downto 0),
 271                 next_ce_i      => lxfncapprox_next_ce_s,
 272                 data_i         => tumbl_data_i_s,
 273                 data_o         => lxfncapprox_out_s,
 274                 bls_i          => tumbl_bls_s
 275         );
 276
 277 -- Reset
 278 dff_reset: dff2
 279         port map
 280         (
 281                 clk_i   => clk_50m,
 282                 d_i     => init_s,
 283                 q_o     => reset_s
 284         );
 285
 286         -- Reset
 287         init_s          <= not init;
 288
 289         -- Signalling
 290         data_i_s        <= data_write_s;
 291
 292         -- Tumbl
 293         tumbl_bls_s     <= i_bls_s when (master_tumbl_xmem_lock_s = '1')
 294                            else tumbl_xmemb_o_s.bls when (tumbl_xmemb_sel_s = '1')
 295                            else "0000";
 296         tumbl_address_s <= address_f_s(14 downto 0) when (master_tumbl_xmem_lock_s = '1')
 297                            else tumbl_xmemb_o_s.addr when (tumbl_xmemb_sel_s = '1')
 298                            else (others => '0');
 299         tumbl_data_i_s  <= data_i_s when (master_tumbl_xmem_lock_s = '1')
 300                            else tumbl_xmemb_o_s.data when (tumbl_xmemb_sel_s = '1')
 301                            else (others => '0');
 302         --
 303         tumbl_xmemb_i_s.int <= '0'; -- No interrupt
 304         -- Enable clken only when available for Tumbl
 305         tumbl_xmemb_i_s.bus_taken <= master_tumbl_xmem_lock_s;
 306         tumbl_xmemb_i_s.bus_wait <= '0';
 307
 308
 309
 310 -- Bus update
 311 memory_bus_logic:
 312         process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_cycle2_s, last_i_rd_s,
 313                 bls_f_s, last_bls_s, data_f_s, data_write_s,
 314                 data_o_s, data_read_s, last_address_s, address_f_s)
 315         begin
 316                 -- Defaults
 317                 next_i_rd_cycle2_s <= '0';
 318                 next_address_hold_s <= '0';
 319
 320                 -- Check if we have chip select
 321                 if cs0_xc_f_s = '1' then
 322
 323                         -- Reading
 324                         if rd_f_s = '1' then
 325                                 -- Internal read
 326                                 if last_rd_s = '0' or (last_address_s /= address_f_s) then
 327                                         i_rd_s <= '1';
 328                                         next_i_rd_cycle2_s <= '1';
 329                                         next_last_i_rd_s  <= '1';
 330                                 elsif i_rd_cycle2_s = '1' then    -- FIXME it seems that some internal
 331                                         i_rd_s <= '1';            -- peripherals demands 2 cycles to read
 332                                         next_last_i_rd_s  <= '1';
 333                                 else
 334                                         i_rd_s            <= '0';
 335                                         next_last_i_rd_s  <= '0';
 336                                 end if;
 337
 338                                 if last_i_rd_s = '1' then
 339                                         -- Latch data we just read - they are valid in this cycle
 340                                         next_data_read_s <= data_o_s;
 341                                 else
 342                                         next_data_read_s <= data_read_s;
 343                                 end if;
 344                         else
 345                         --      -- Not reading, anything goes
 346                         --      data_read_s       <= (others => 'X');
 347                                 next_data_read_s  <= data_read_s;
 348                                 i_rd_s            <= '0';
 349                                 next_last_i_rd_s  <= '0';
 350                         end if;
 351
 352                         next_last_rd_s            <= rd_f_s;
 353
 354                         -- Data for write are captured only when BLS signals are stable
 355                         if bls_f_s /= "0000" then
 356                                 next_data_write_s <= data_f_s;
 357                                 next_address_hold_s <= '1';
 358                         else
 359                                 next_data_write_s <= data_write_s;
 360                         end if;
 361
 362                         if (bls_f_s /= "0000") or (rd_f_s = '1') then
 363                                 next_last_address_s <= address_f_s;
 364                         else
 365                                 next_last_address_s <= last_address_s;
 366                         end if;
 367                 else
 368                         next_last_rd_s <= '0';
 369                         i_rd_s <= '0';
 370                         next_last_i_rd_s <= '0';
 371
 372                         next_i_bls_s <= "0000";
 373                         next_data_write_s <= data_write_s;
 374                         next_data_read_s  <= data_read_s;
 375                         next_last_address_s <= last_address_s;
 376                 end if;
 377
 378                 -- Data for write are captured at/before BLS signals are negated
 379                 -- and actual write cycle takes place exacly after BLS negation
 380                 if ((last_bls_s and not bls_f_s) /= "0000") or
 381                     ((last_bls_s /= "0000") and (cs0_xc_f_s = '0')) then
 382                         next_i_bls_s <= last_bls_s;
 383                         next_last_bls_s   <= "0000";
 384                         next_address_hold_s <= '1';
 385                 else
 386                         next_i_bls_s <= "0000";
 387                         if cs0_xc_f_s = '1' then
 388                                 next_last_bls_s <= bls_f_s;
 389                         else
 390                                 next_last_bls_s <= "0000" ;
 391                         end if;
 392                 end if;
 393
 394         end process;
 395
 396 -- Bus update
 397 memory_bus_update:
 398         process
 399         begin
 400
 401                 wait until clk_50m = '1' and clk_50m'event;
 402
 403                 address_hold_s <= next_address_hold_s;
 404
 405                 -- Synchronized external signals with main clock domain
 406                 cs0_xc_f_s     <= not cs0_xc;
 407                 bls_f_s        <= not bls;
 408                 rd_f_s         <= not rd;
 409                 data_f_s       <= data;
 410                 if address_hold_s = '0' then
 411                         address_f_s <= address;
 412                 else
 413                         address_f_s <= next_last_address_s;
 414                 end if;
 415
 416                 -- Synchronoust state andvance to next period
 417                 last_bls_s     <= next_last_bls_s;
 418                 last_rd_s      <= next_last_rd_s;
 419                 i_bls_s        <= next_i_bls_s;
 420                 -- i_rd_s         <= next_i_rd_s;
 421                 i_rd_cycle2_s  <= next_i_rd_cycle2_s;
 422                 last_i_rd_s    <= next_last_i_rd_s;
 423                 data_write_s   <= next_data_write_s;
 424                 last_address_s <= next_last_address_s;
 425                 data_read_s    <= next_data_read_s;
 426                 --
 427                 -- ======================================================
 428                 --  TUMBL BUS
 429                 -- ======================================================
 430
 431                 -- Just copy these to their desired next state
 432                 irc_proc_ce_s <= irc_proc_next_ce_s;
 433                 lxmaster_ce_s <= lxmaster_next_ce_s;
 434                 lxfncapprox_ce_s <= lxfncapprox_next_ce_s;
 435
 436         end process;
 437
 438 -- Do the actual wiring here
 439 memory_bus_wiring:
 440         process(cs0_xc_f_s, i_bls_s, address_f_s, tumbl_out_s, meas_out_s, master_tumbl_xmem_out_s)
 441         begin
 442
 443                 -- Inactive by default
 444                 tumbl_ce_s             <= '0';
 445                 meas_ce_s              <= '0';
 446                 master_tumbl_xmem_ce_s <= '0';
 447                 data_o_s               <= (others => '0');
 448
 449                 if cs0_xc_f_s = '1' or i_bls_s /= "0000" then
 450
 451                         -- Memory Map (16-bit address @ 32-bit each)
 452
 453                         -- Each address is seen as 32-bit entry now
 454                         -- 0x0000 - 0x0FFF: Tumbl IMEM / DMEM
 455                         -- 0x1FFC - 0x1FFF: Measurement
 456                         -- 0x8000 - 0x8FFF: Tumbl BUS
 457
 458                         if address_f_s < "0001000000000000" then                  -- Tumbl
 459                                 tumbl_ce_s             <= '1';
 460                                 data_o_s               <= tumbl_out_s;
 461                         elsif address_f_s(15 downto 2) = "00011111111111" then    -- Measurement
 462                                 meas_ce_s              <= '1';
 463                                 data_o_s               <= meas_out_s;
 464                         elsif address_f_s(15) = '1' then                          -- Tumbl External BUS
 465                                 master_tumbl_xmem_ce_s <= '1';
 466                                 data_o_s               <= master_tumbl_xmem_out_s;
 467                         end if;
 468
 469                 end if;
 470
 471         end process;
 472
 473 -- If RD and BLS is not high, we must keep DATA at high impedance
 474 -- or the FPGA collides with SDRAM (damaging each other)
 475 memory_bus_out:
 476         process(cs0_xc, rd, data_read_s)
 477         begin
 478
 479                 -- CS0 / RD / BLS are active LOW
 480                 if cs0_xc = '0' and rd = '0' then
 481                         -- Don't risk flipping (between data_o_s and latched data_read_s, it's better to wait)
 482                         -- Maybe check this later.
 483                         -- if last_i_rd_s = '1' then
 484                         --   data <= data_o_s;
 485                         -- else
 486                         data <= data_read_s;
 487                         -- end if;
 488                 else
 489                         -- IMPORTANT!!!
 490                         data <= (others => 'Z');
 491                 end if;
 492
 493         end process;
 494
 495 -- Outputs from Tumbl (enabling and address muxing) and Master CPU
 496 tumbl_bus_o:
 497         process(tumbl_xmemb_sel_s, tumbl_xmemb_o_s, master_tumbl_xmem_ce_s, address_f_s, i_rd_s, i_bls_s)
 498                 variable addr_v : std_logic_vector(14 downto 0); -- This space is visible by both (32-bit)
 499                 variable sel_v  : std_logic;
 500         begin
 501
 502                 -- Defaults
 503                 irc_proc_next_ce_s        <= '0';
 504                 lxmaster_next_ce_s        <= '0';
 505                 lxfncapprox_next_ce_s     <= '0';
 506                 master_tumbl_xmem_lock_s  <= '0';
 507                 --
 508                 addr_v                    := (others => '0');
 509                 sel_v                     := '0';
 510
 511                 -- Check who is accessing
 512                 if master_tumbl_xmem_ce_s = '1' and (i_rd_s = '1' or i_bls_s /= "0000") then
 513                         -- Master blocks Tumbl
 514                         master_tumbl_xmem_lock_s <= '1';
 515                         addr_v                   := address_f_s(14 downto 0);
 516                         sel_v                    := '1';
 517                 else
 518                         addr_v                   := tumbl_xmemb_o_s.addr;
 519                         sel_v                    := '1';
 520                 end if;
 521
 522                 if sel_v = '1' then
 523                         -- IRC:       0x0800 - 0x081F (32-bit address)
 524                         -- LX FNC AP: 0x0C00 - 0x0C1F (32-bit address)
 525                         -- LX MASTER: 0x1000 - 0x17FF (32-bit address)
 526                         if addr_v(14 downto 5) = "0001000000" then
 527                                 irc_proc_next_ce_s     <= '1';
 528                         elsif addr_v(14 downto 5) = "0001100000" then
 529                                 lxfncapprox_next_ce_s  <= '1';
 530                         elsif addr_v(14 downto 11) = "0010" then
 531                                 lxmaster_next_ce_s     <= '1';
 532                         end if;
 533                 end if;
 534
 535         end process;
 536
 537 -- Inputs to Tumbl (enabling and address muxing)
 538 tumbl_bus_i:
 539         process(irc_proc_ce_s, irc_proc_out_s, lxmaster_ce_s, lxmaster_out_s,
 540                 lxfncapprox_ce_s, lxfncapprox_out_s, tumbl_xmemb_i_s)
 541         begin
 542
 543                 tumbl_xmemb_i_s.data  <= (others => 'X');
 544
 545                 -- NOTE: This is input to Tumbl EXEQ - with MUL instruction for input > 18-bit,
 546                 -- (i.e. more DSPs in a sequence), this already has tough timing constraints
 547                 -- and SmartXplorer has to be used with XiSE or use Synplify.
 548                 if irc_proc_ce_s = '1' then
 549                         tumbl_xmemb_i_s.data <= irc_proc_out_s;
 550                 elsif lxmaster_ce_s = '1' then
 551                         tumbl_xmemb_i_s.data(15 downto 0)  <= lxmaster_out_s;
 552                         tumbl_xmemb_i_s.data(31 downto 16) <= (others => '0');
 553                 elsif lxfncapprox_ce_s = '1' then
 554                         tumbl_xmemb_i_s.data <= lxfncapprox_out_s;
 555                 end if;
 556
 557                 master_tumbl_xmem_out_s <= tumbl_xmemb_i_s.data;
 558
 559         end process;
 560
 561 events_logic:
 562         process(lxmaster_rx_done_r, lxmaster_rx_done_last_r)
 563         begin
 564                 event_jk_j <= lxmaster_rx_done_r or lxmaster_rx_done_last_r;
 565                 lxmaster_rx_done_last_s <= lxmaster_rx_done_r;
 566         end process;
 567
 568 events_update:
 569         process
 570         begin
 571                 wait until clk_50m = '1' and clk_50m'event;
 572
 573                 lxmaster_rx_done_r <= lxmaster_rx_done_s;
 574                 lxmaster_rx_done_last_r <= lxmaster_rx_done_last_s;
 575         end process;
 576
 577 end Behavioral;
 578