hw/lx_rocon_top.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5 use ieee.numeric_std.all;
   6
   7 library unisim;
   8 use unisim.vcomponents.all;
   9
  10 use work.mbl_pkg.all;
  11 use work.lx_rocon_pkg.all;
  12
  13 -- lx_rocon_top - wires the modules with the outside world
  14
  15 -- ======================================================
  16 --  MASTER CPU EXTERNAL MEMORY BUS
  17 -- ======================================================
  18 --
  19 -- Master cpu memory bus has the following wires:
  20 --
  21 -- - address[15..0]          The address, used to mark chip enable
  22 -- - data_in[31..0]          The data coming to bus
  23 -- - data_out[31..0]         The data coming from bus, multiplexed
  24 -- - bls[3..0]               Write enable for respective bytes
  25
  26 entity lx_rocon_top is
  27         port
  28         (
  29                 -- External
  30                 --clk_cpu     : in std_logic;
  31                 clk_50m     : in std_logic;
  32                 --
  33                 cs0_xc      : in std_logic;
  34                 --
  35                 rd          : in std_logic;
  36                 bls         : in std_logic_vector(3 downto 0);
  37                 address     : in std_logic_vector(15 downto 0);
  38                 data        : inout std_logic_vector(31 downto 0);
  39                 --
  40                 irc0_a      : in std_logic;
  41                 irc0_b      : in std_logic;
  42                 irc0_index  : in std_logic;
  43                 irc0_mark   : in std_logic;
  44                 --
  45                 irc1_a      : in std_logic;
  46                 irc1_b      : in std_logic;
  47                 irc1_index  : in std_logic;
  48                 irc1_mark   : in std_logic;
  49                 --
  50                 irc2_a      : in std_logic;
  51                 irc2_b      : in std_logic;
  52                 irc2_index  : in std_logic;
  53                 irc2_mark   : in std_logic;
  54                 --
  55                 irc3_a      : in std_logic;
  56                 irc3_b      : in std_logic;
  57                 irc3_index  : in std_logic;
  58                 irc3_mark   : in std_logic;
  59                 --
  60                 irc4_a      : in std_logic;
  61                 irc4_b      : in std_logic;
  62                 irc4_index  : in std_logic;
  63                 irc4_mark   : in std_logic;
  64                 --
  65                 irc5_a      : in std_logic;
  66                 irc5_b      : in std_logic;
  67                 irc5_index  : in std_logic;
  68                 irc5_mark   : in std_logic;
  69                 --
  70                 irc6_a      : in std_logic;
  71                 irc6_b      : in std_logic;
  72                 irc6_index  : in std_logic;
  73                 irc6_mark   : in std_logic;
  74                 --
  75                 irc7_a      : in std_logic;
  76                 irc7_b      : in std_logic;
  77                 irc7_index  : in std_logic;
  78                 irc7_mark   : in std_logic;
  79                 --
  80                 init        : in std_logic;
  81                 --
  82                 s1_clk_in   : in std_logic;
  83                 s1_miso     : in std_logic;
  84                 s1_sync_in  : in std_logic;
  85                 --
  86                 s1_clk_out  : out std_logic;
  87                 s1_mosi     : out std_logic;
  88                 s1_sync_out : out std_logic;
  89                 -- signal connected to external JK FF
  90                 event_jk_j  : out std_logic
  91         );
  92 end lx_rocon_top;
  93
  94 architecture Behavioral of lx_rocon_top is
  95
  96         -- Reset signal
  97         signal reset_s                  : std_logic;
  98         signal init_s                   : std_logic;
  99         -- Peripherals on the memory buses
 100         -- Master to Tumbl DMEM / IMEM (Master)
 101         signal tumbl_out_s              : std_logic_vector(31 downto 0);
 102         signal tumbl_ce_s               : std_logic;
 103         -- Measurement (Master)
 104         signal meas_out_s               : std_logic_vector(31 downto 0);
 105         signal meas_ce_s                : std_logic;
 106         -- Master to Tumbl XMEM
 107         signal master_tumbl_xmem_out_s  : std_logic_vector(31 downto 0);
 108         signal master_tumbl_xmem_ce_s   : std_logic;
 109         signal master_tumbl_xmem_lock_s : std_logic;
 110         -- IRC (Tumbl)
 111         signal irc_proc_out_s            : std_logic_vector(31 downto 0);
 112         signal irc_proc_ce_s             : std_logic;
 113         signal irc_proc_next_ce_s        : std_logic;
 114         -- LX Master (Tumbl)
 115         signal lxmaster_out_s           : std_logic_vector(15 downto 0);
 116         signal lxmaster_ce_s            : std_logic;
 117         signal lxmaster_next_ce_s       : std_logic;
 118         -- LX function approximation
 119         signal lxfncapprox_out_s        : std_logic_vector(31 downto 0);
 120         signal lxfncapprox_ce_s         : std_logic;
 121         signal lxfncapprox_next_ce_s    : std_logic;
 122         -- Signals for external bus transmission
 123         signal data_i_s                 : std_logic_vector(31 downto 0);
 124         signal data_o_s                 : std_logic_vector(31 downto 0);
 125         -- Signals for internal transaction
 126         signal last_address_s           : std_logic_vector(15 downto 0);
 127         signal next_last_address_s      : std_logic_vector(15 downto 0);
 128         signal next_address_hold_s      : std_logic;
 129         signal address_hold_s           : std_logic;
 130         signal last_rd_s                : std_logic;
 131         signal next_last_rd_s           : std_logic;
 132         signal last_bls_s               : std_logic_vector(3 downto 0); -- prev bls_f_s (active 1)
 133         signal next_last_bls_s          : std_logic_vector(3 downto 0);
 134
 135         -- Reading logic for Master CPU:
 136         -- Broadcast rd only till ta (transaction acknowledge)
 137         -- is received, then latch the data till the state of
 138         -- rd or address changes
 139         --
 140         -- Data latching is synchronous - it's purpose is to
 141         -- provide stable data for CPU on the bus
 142         signal cs0_xc_f_s          : std_logic;
 143         signal rd_f_s              : std_logic; -- Filtered RD
 144         signal i_rd_s              : std_logic; -- Internal bus RD (active 1)
 145         -- signal next_i_rd_s         : std_logic;
 146         signal last_i_rd_s         : std_logic; -- Delayed RD bus, used for latching
 147         signal next_last_i_rd_s    : std_logic;
 148         signal i_rd_cycle2_s       : std_logic; -- Some internal subsystems provide
 149         signal next_i_rd_cycle2_s  : std_logic; -- data only after 2 cycles
 150         --
 151         signal address_f_s         : std_logic_vector(15 downto 0); -- Filtered address
 152         --
 153         signal data_f_s            : std_logic_vector(31 downto 0); -- Filterred input data
 154         --
 155         signal data_read_s         : std_logic_vector(31 downto 0); -- Latched read data
 156         signal next_data_read_s    : std_logic_vector(31 downto 0);
 157
 158         -- Writing logic:
 159         signal bls_f_s             : std_logic_vector(3 downto 0); -- Filtered BLS (active 1)
 160         signal i_bls_s             : std_logic_vector(3 downto 0); -- Internal BLS (active 1)
 161         signal next_i_bls_s        : std_logic_vector(3 downto 0);
 162         --
 163         signal data_write_s        : std_logic_vector(31 downto 0); -- Data broadcasted to write
 164         signal next_data_write_s   : std_logic_vector(31 downto 0);
 165
 166         -- Tumbl:
 167         signal tumbl_bls_s         : std_logic_vector(3 downto 0);
 168         signal tumbl_address_s     : std_logic_vector(14 downto 0);
 169         signal tumbl_data_i_s      : std_logic_vector(31 downto 0);
 170         --
 171         signal tumbl_xmemb_o_s     : CORE2DMEMB_Type;
 172         signal tumbl_xmemb_i_s     : DMEMB2CORE_Type;
 173         signal tumbl_xmemb_sel_s   : std_logic;
 174         -- Interrupt event sources and processing
 175         signal lxmaster_rx_done_s  : std_logic;
 176         signal lxmaster_rx_done_r  : std_logic;
 177         signal lxmaster_rx_done_last_s : std_logic;
 178         signal lxmaster_rx_done_last_r : std_logic;
 179
 180         -- signal s0   : std_logic;
 181         -- signal s1   : std_logic;
 182         -- signal s2   : std_logic;
 183
 184         -- XST attributes
 185         attribute REGISTER_DUPLICATION : string;
 186         attribute REGISTER_DUPLICATION of rd : signal is "NO";
 187         attribute REGISTER_DUPLICATION of rd_f_s : signal is "NO";
 188         attribute REGISTER_DUPLICATION of bls : signal is "NO";
 189         attribute REGISTER_DUPLICATION of bls_f_s : signal is "NO";
 190         attribute REGISTER_DUPLICATION of address : signal is "NO";
 191         attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
 192         attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
 193
 194 begin
 195
 196 -- Tumbl coprocessor
 197 memory_bus_tumbl: bus_tumbl
 198         port map
 199         (
 200                 clk_i          => clk_50m,
 201                 reset_i        => reset_s,
 202                 ce_i           => tumbl_ce_s,
 203                 bls_i          => i_bls_s,
 204                 address_i      => address_f_s(11 downto 0),
 205                 data_i         => data_i_s,
 206                 data_o         => tumbl_out_s,
 207                 --
 208                 xmemb_o        => tumbl_xmemb_o_s,
 209                 xmemb_i        => tumbl_xmemb_i_s,
 210                 xmemb_sel_o    => tumbl_xmemb_sel_s
 211         );
 212
 213 -- Measurement
 214 memory_bus_measurement: bus_measurement
 215         port map
 216         (
 217                 clk_i     => clk_50m,
 218                 reset_i   => reset_s,
 219                 ce_i      => meas_ce_s,
 220                 address_i => address_f_s(1 downto 0),
 221                 bls_i     => i_bls_s,
 222                 data_i    => data_i_s,
 223                 data_o    => meas_out_s
 224         );
 225
 226 -- IRC interconnect
 227 memory_bus_irc: bus_irc
 228         port map
 229         (
 230                 reset_i        => reset_s,
 231                 --
 232                 clk_i          => clk_50m,
 233                 address_i      => tumbl_address_s(4 downto 0),
 234                 next_ce_i      => irc_proc_next_ce_s,
 235                 data_i         => tumbl_data_i_s,
 236                 data_o         => irc_proc_out_s,
 237                 bls_i          => tumbl_bls_s,
 238                 --
 239                 irc_i(0).a     => irc0_a,
 240                 irc_i(0).b     => irc0_b,
 241                 irc_i(0).index => irc0_index,
 242                 irc_i(0).mark  => irc0_mark,
 243                 --
 244                 irc_i(1).a     => irc1_a,
 245                 irc_i(1).b     => irc1_b,
 246                 irc_i(1).index => irc1_index,
 247                 irc_i(1).mark  => irc1_mark,
 248                 --
 249                 irc_i(2).a     => irc2_a,
 250                 irc_i(2).b     => irc2_b,
 251                 irc_i(2).index => irc2_index,
 252                 irc_i(2).mark  => irc2_mark,
 253                 --
 254                 irc_i(3).a     => irc3_a,
 255                 irc_i(3).b     => irc3_b,
 256                 irc_i(3).index => irc3_index,
 257                 irc_i(3).mark  => irc3_mark,
 258                 --
 259                 irc_i(4).a     => irc4_a,
 260                 irc_i(4).b     => irc4_b,
 261                 irc_i(4).index => irc4_index,
 262                 irc_i(4).mark  => irc4_mark,
 263                 --
 264                 irc_i(5).a     => irc5_a,
 265                 irc_i(5).b     => irc5_b,
 266                 irc_i(5).index => irc5_index,
 267                 irc_i(5).mark  => irc5_mark,
 268                 --
 269                 irc_i(6).a     => irc6_a,
 270                 irc_i(6).b     => irc6_b,
 271                 irc_i(6).index => irc6_index,
 272                 irc_i(6).mark  => irc6_mark,
 273                 --
 274                 irc_i(7).a     => irc7_a,
 275                 irc_i(7).b     => irc7_b,
 276                 irc_i(7).index => irc7_index,
 277                 irc_i(7).mark  => irc7_mark
 278         );
 279
 280 -- LX Master
 281 memory_bus_lxmaster: bus_lxmaster
 282         port map
 283         (
 284                 reset_i        => reset_s,
 285                 --
 286                 clk_i          => clk_50m,
 287                 address_i      => tumbl_address_s(10 downto 0),
 288                 next_ce_i      => lxmaster_next_ce_s,
 289                 data_i         => tumbl_data_i_s(15 downto 0),
 290                 data_o         => lxmaster_out_s,
 291                 bls_i          => tumbl_bls_s(1 downto 0),
 292                 --
 293                 rx_done_o      => lxmaster_rx_done_s,
 294                 --
 295                 clock_i        => s1_clk_in,
 296                 miso_i         => s1_miso,
 297                 sync_i         => s1_sync_in,
 298                 --
 299                 clock_o        => s1_clk_out,
 300                 mosi_o         => s1_mosi,
 301                 sync_o         => s1_sync_out
 302                 --
 303                 -- clock_i        => s0,
 304                 -- miso_i         => s1,
 305                 -- sync_i         => not s2,
 306                 --
 307                 -- clock_o        => s0,
 308                 -- mosi_o         => s1,
 309                 -- sync_o         => s2
 310         );
 311
 312         -- s1_clk_out      <= s0;
 313         -- s1_mosi         <= s1;
 314         -- s1_sync_out     <= s2;
 315
 316
 317 function_approx: component lx_fncapprox
 318         port map
 319         (
 320                 reset_i      => reset_s,
 321                 clk_i        => clk_50m,
 322                 -- Data bus
 323                 address_i      => tumbl_address_s(4 downto 0),
 324                 next_ce_i      => lxfncapprox_next_ce_s,
 325                 data_i         => tumbl_data_i_s,
 326                 data_o         => lxfncapprox_out_s,
 327                 bls_i          => tumbl_bls_s
 328         );
 329
 330 -- Reset
 331 dff_reset: dff2
 332         port map
 333         (
 334                 clk_i   => clk_50m,
 335                 d_i     => init_s,
 336                 q_o     => reset_s
 337         );
 338
 339         -- Reset
 340         init_s          <= not init;
 341
 342         -- Signalling
 343         data_i_s        <= data_write_s;
 344
 345         -- Tumbl
 346         tumbl_bls_s     <= i_bls_s when (master_tumbl_xmem_lock_s = '1')
 347                            else tumbl_xmemb_o_s.bls when (tumbl_xmemb_sel_s = '1')
 348                            else "0000";
 349         tumbl_address_s <= address_f_s(14 downto 0) when (master_tumbl_xmem_lock_s = '1')
 350                            else tumbl_xmemb_o_s.addr when (tumbl_xmemb_sel_s = '1')
 351                            else (others => '0');
 352         tumbl_data_i_s  <= data_i_s when (master_tumbl_xmem_lock_s = '1')
 353                            else tumbl_xmemb_o_s.data when (tumbl_xmemb_sel_s = '1')
 354                            else (others => '0');
 355         --
 356         tumbl_xmemb_i_s.int <= '0'; -- No interrupt
 357         -- Enable clken only when available for Tumbl
 358         tumbl_xmemb_i_s.clken <= not master_tumbl_xmem_lock_s;
 359
 360
 361 -- Bus update
 362 memory_bus_logic:
 363         process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_cycle2_s, last_i_rd_s,
 364                 bls_f_s, last_bls_s, data_f_s, data_write_s,
 365                 data_o_s, data_read_s, last_address_s, address_f_s)
 366         begin
 367                 -- Defaults
 368                 next_i_rd_cycle2_s <= '0';
 369                 next_address_hold_s <= '0';
 370
 371                 -- Check if we have chip select
 372                 if cs0_xc_f_s = '1' then
 373
 374                         -- Reading
 375                         if rd_f_s = '1' then
 376                                 -- Internal read
 377                                 if last_rd_s = '0' or (last_address_s /= address_f_s) then
 378                                         i_rd_s <= '1';
 379                                         next_i_rd_cycle2_s <= '1';
 380                                         next_last_i_rd_s  <= '1';
 381                                 elsif i_rd_cycle2_s = '1' then    -- FIXME it seems that some internal
 382                                         i_rd_s <= '1';            -- peripherals demands 2 cycles to read
 383                                         next_last_i_rd_s  <= '1';
 384                                 else
 385                                         i_rd_s            <= '0';
 386                                         next_last_i_rd_s  <= '0';
 387                                 end if;
 388
 389                                 if last_i_rd_s = '1' then
 390                                         -- Latch data we just read - they are valid in this cycle
 391                                         next_data_read_s <= data_o_s;
 392                                 else
 393                                         next_data_read_s <= data_read_s;
 394                                 end if;
 395                         else
 396                         --      -- Not reading, anything goes
 397                         --      data_read_s       <= (others => 'X');
 398                                 next_data_read_s  <= data_read_s;
 399                                 i_rd_s            <= '0';
 400                                 next_last_i_rd_s  <= '0';
 401                         end if;
 402
 403                         next_last_rd_s            <= rd_f_s;
 404
 405                         -- Data for write are captured only when BLS signals are stable
 406                         if bls_f_s /= "0000" then
 407                                 next_data_write_s <= data_f_s;
 408                                 next_address_hold_s <= '1';
 409                         else
 410                                 next_data_write_s <= data_write_s;
 411                         end if;
 412
 413                         if (bls_f_s /= "0000") or (rd_f_s = '1') then
 414                                 next_last_address_s <= address_f_s;
 415                         else
 416                                 next_last_address_s <= last_address_s;
 417                         end if;
 418                 else
 419                         next_last_rd_s <= '0';
 420                         i_rd_s <= '0';
 421                         next_last_i_rd_s <= '0';
 422
 423                         next_i_bls_s <= "0000";
 424                         next_data_write_s <= data_write_s;
 425                         next_data_read_s  <= data_read_s;
 426                         next_last_address_s <= last_address_s;
 427                 end if;
 428
 429                 -- Data for write are captured at/before BLS signals are negated
 430                 -- and actual write cycle takes place exacly after BLS negation
 431                 if ((last_bls_s and not bls_f_s) /= "0000") or
 432                     ((last_bls_s /= "0000") and (cs0_xc_f_s = '0')) then
 433                         next_i_bls_s <= last_bls_s;
 434                         next_last_bls_s   <= "0000";
 435                         next_address_hold_s <= '1';
 436                 else
 437                         next_i_bls_s <= "0000";
 438                         if cs0_xc_f_s = '1' then
 439                                 next_last_bls_s <= bls_f_s;
 440                         else
 441                                 next_last_bls_s <= "0000" ;
 442                         end if;
 443                 end if;
 444
 445         end process;
 446
 447 -- Bus update
 448 memory_bus_update:
 449         process
 450         begin
 451
 452                 wait until clk_50m = '1' and clk_50m'event;
 453
 454                 address_hold_s <= next_address_hold_s;
 455
 456                 -- Synchronized external signals with main clock domain
 457                 cs0_xc_f_s     <= not cs0_xc;
 458                 bls_f_s        <= not bls;
 459                 rd_f_s         <= not rd;
 460                 data_f_s       <= data;
 461                 if address_hold_s = '0' then
 462                         address_f_s <= address;
 463                 else
 464                         address_f_s <= next_last_address_s;
 465                 end if;
 466
 467                 -- Synchronoust state andvance to next period
 468                 last_bls_s     <= next_last_bls_s;
 469                 last_rd_s      <= next_last_rd_s;
 470                 i_bls_s        <= next_i_bls_s;
 471                 -- i_rd_s         <= next_i_rd_s;
 472                 i_rd_cycle2_s  <= next_i_rd_cycle2_s;
 473                 last_i_rd_s    <= next_last_i_rd_s;
 474                 data_write_s   <= next_data_write_s;
 475                 last_address_s <= next_last_address_s;
 476                 data_read_s    <= next_data_read_s;
 477                 --
 478                 -- ======================================================
 479                 --  TUMBL BUS
 480                 -- ======================================================
 481
 482                 -- Just copy these to their desired next state
 483                 irc_proc_ce_s <= irc_proc_next_ce_s;
 484                 lxmaster_ce_s <= lxmaster_next_ce_s;
 485                 lxfncapprox_ce_s <= lxfncapprox_next_ce_s;
 486
 487         end process;
 488
 489 -- Do the actual wiring here
 490 memory_bus_wiring:
 491         process(cs0_xc_f_s, i_bls_s, address_f_s, tumbl_out_s, meas_out_s, master_tumbl_xmem_out_s)
 492         begin
 493
 494                 -- Inactive by default
 495                 tumbl_ce_s             <= '0';
 496                 meas_ce_s              <= '0';
 497                 master_tumbl_xmem_ce_s <= '0';
 498                 data_o_s               <= (others => '0');
 499
 500                 if cs0_xc_f_s = '1' or i_bls_s /= "0000" then
 501
 502                         -- Memory Map (16-bit address @ 32-bit each)
 503
 504                         -- Each address is seen as 32-bit entry now
 505                         -- 0x0000 - 0x0FFF: Tumbl IMEM / DMEM
 506                         -- 0x1FFC - 0x1FFF: Measurement
 507                         -- 0x8000 - 0x8FFF: Tumbl BUS
 508
 509                         if address_f_s < "0001000000000000" then                  -- Tumbl
 510                                 tumbl_ce_s             <= '1';
 511                                 data_o_s               <= tumbl_out_s;
 512                         elsif address_f_s(15 downto 2) = "00011111111111" then    -- Measurement
 513                                 meas_ce_s              <= '1';
 514                                 data_o_s               <= meas_out_s;
 515                         elsif address_f_s(15) = '1' then                          -- Tumbl External BUS
 516                                 master_tumbl_xmem_ce_s <= '1';
 517                                 data_o_s               <= master_tumbl_xmem_out_s;
 518                         end if;
 519
 520                 end if;
 521
 522         end process;
 523
 524 -- If RD and BLS is not high, we must keep DATA at high impedance
 525 -- or the FPGA collides with SDRAM (damaging each other)
 526 memory_bus_out:
 527         process(cs0_xc, rd, data_read_s)
 528         begin
 529
 530                 -- CS0 / RD / BLS are active LOW
 531                 if cs0_xc = '0' and rd = '0' then
 532                         -- Don't risk flipping (between data_o_s and latched data_read_s, it's better to wait)
 533                         -- Maybe check this later.
 534                         -- if last_i_rd_s = '1' then
 535                         --   data <= data_o_s;
 536                         -- else
 537                         data <= data_read_s;
 538                         -- end if;
 539                 else
 540                         -- IMPORTANT!!!
 541                         data <= (others => 'Z');
 542                 end if;
 543
 544         end process;
 545
 546 -- Outputs from Tumbl (enabling and address muxing) and Master CPU
 547 tumbl_bus_o:
 548         process(tumbl_xmemb_sel_s, tumbl_xmemb_o_s, master_tumbl_xmem_ce_s, address_f_s, i_rd_s, i_bls_s)
 549                 variable addr_v : std_logic_vector(14 downto 0); -- This space is visible by both (32-bit)
 550                 variable sel_v  : std_logic;
 551         begin
 552
 553                 -- Defaults
 554                 irc_proc_next_ce_s        <= '0';
 555                 lxmaster_next_ce_s        <= '0';
 556                 lxfncapprox_next_ce_s     <= '0';
 557                 master_tumbl_xmem_lock_s  <= '0';
 558                 --
 559                 addr_v                    := (others => '0');
 560                 sel_v                     := '0';
 561
 562                 -- Check who is accessing
 563                 if master_tumbl_xmem_ce_s = '1' and (i_rd_s = '1' or i_bls_s /= "0000") then
 564                         -- Master blocks Tumbl
 565                         master_tumbl_xmem_lock_s <= '1';
 566                         addr_v                   := address_f_s(14 downto 0);
 567                         sel_v                    := '1';
 568                 else
 569                         addr_v                   := tumbl_xmemb_o_s.addr;
 570                         sel_v                    := '1';
 571                 end if;
 572
 573                 if sel_v = '1' then
 574                         -- IRC:       0x0800 - 0x081F (32-bit address)
 575                         -- LX FNC AP: 0x0C00 - 0x0C1F (32-bit address)
 576                         -- LX MASTER: 0x1000 - 0x17FF (32-bit address)
 577                         if addr_v(14 downto 5) = "0001000000" then
 578                                 irc_proc_next_ce_s     <= '1';
 579                         elsif addr_v(14 downto 5) = "0001100000" then
 580                                 lxfncapprox_next_ce_s  <= '1';
 581                         elsif addr_v(14 downto 11) = "0010" then
 582                                 lxmaster_next_ce_s     <= '1';
 583                         end if;
 584                 end if;
 585
 586         end process;
 587
 588 -- Inputs to Tumbl (enabling and address muxing)
 589 tumbl_bus_i:
 590         process(irc_proc_ce_s, irc_proc_out_s, lxmaster_ce_s, lxmaster_out_s,
 591                 lxfncapprox_ce_s, lxfncapprox_out_s, tumbl_xmemb_i_s)
 592         begin
 593
 594                 tumbl_xmemb_i_s.data  <= (others => 'X');
 595
 596                 -- NOTE: This is input to Tumbl EXEQ - with MUL instruction for input > 18-bit,
 597                 -- (i.e. more DSPs in a sequence), this already has tough timing constraints
 598                 -- and SmartXplorer has to be used with XiSE or use Synplify.
 599                 if irc_proc_ce_s = '1' then
 600                         tumbl_xmemb_i_s.data <= irc_proc_out_s;
 601                 elsif lxmaster_ce_s = '1' then
 602                         tumbl_xmemb_i_s.data(15 downto 0)  <= lxmaster_out_s;
 603                         tumbl_xmemb_i_s.data(31 downto 16) <= (others => '0');
 604                 elsif lxfncapprox_ce_s = '1' then
 605                         tumbl_xmemb_i_s.data <= lxfncapprox_out_s;
 606                 end if;
 607
 608                 master_tumbl_xmem_out_s <= tumbl_xmemb_i_s.data;
 609
 610         end process;
 611
 612 events_logic:
 613         process(lxmaster_rx_done_r, lxmaster_rx_done_last_r)
 614         begin
 615                 event_jk_j <= lxmaster_rx_done_r or lxmaster_rx_done_last_r;
 616                 lxmaster_rx_done_last_s <= lxmaster_rx_done_r;
 617         end process;
 618
 619 events_update:
 620         process
 621         begin
 622                 wait until clk_50m = '1' and clk_50m'event;
 623
 624                 lxmaster_rx_done_r <= lxmaster_rx_done_s;
 625                 lxmaster_rx_done_last_r <= lxmaster_rx_done_last_s;
 626         end process;
 627
 628 end Behavioral;
 629