hw/bus_irc.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5 use ieee.numeric_std.all;
   6 use work.lx_rocon_pkg.all;
   7
   8 -- IRC bus interconnect: memory region for IRC
   9
  10 entity bus_irc is
  11         port
  12         (
  13                 clk_i        : in std_logic;
  14                 reset_i      : in std_logic;
  15                 -- Address (needs just last 4 bits, rest is wired to CE)
  16                 address_i    : in std_logic_vector(3 downto 0);
  17                 ce_i         : in std_logic;
  18                 -- Data bus
  19                 data_i       : in std_logic; -- 1 bit input
  20                 data_o       : out std_logic_vector(31 downto 0);
  21                 -- Bus signals
  22                 rd_i         : in std_logic;
  23                 ta_o         : out std_logic;
  24                 wr_i         : in std_logic;
  25                 -- Signals for IRC
  26                 irc1_a_i     : in std_logic;
  27                 irc1_b_i     : in std_logic;
  28                 irc1_index_i : in std_logic;
  29                 irc1_mark_i  : in std_logic;
  30                 --
  31                 irc2_a_i     : in std_logic;
  32                 irc2_b_i     : in std_logic;
  33                 irc2_index_i : in std_logic;
  34                 irc2_mark_i  : in std_logic;
  35                 --
  36                 irc3_a_i     : in std_logic;
  37                 irc3_b_i     : in std_logic;
  38                 irc3_index_i : in std_logic;
  39                 irc3_mark_i  : in std_logic;
  40                 --
  41                 irc4_a_i     : in std_logic;
  42                 irc4_b_i     : in std_logic;
  43                 irc4_index_i : in std_logic;
  44                 irc4_mark_i  : in std_logic
  45         );
  46 end bus_irc;
  47
  48 architecture Behavioral of bus_irc is
  49
  50         -- Multiplexer signals
  51         signal irc1_out_s : std_logic_vector(31 downto 0);
  52         signal irc1_ta_s  : std_logic;
  53         signal irc1_ce_s  : std_logic_vector(1 downto 0);
  54
  55         signal irc2_out_s : std_logic_vector(31 downto 0);
  56         signal irc2_ta_s  : std_logic;
  57         signal irc2_ce_s  : std_logic_vector(1 downto 0);
  58
  59         signal irc3_out_s : std_logic_vector(31 downto 0);
  60         signal irc3_ta_s  : std_logic;
  61         signal irc3_ce_s  : std_logic_vector(1 downto 0);
  62
  63         signal irc4_out_s : std_logic_vector(31 downto 0);
  64         signal irc4_ta_s  : std_logic;
  65         signal irc4_ce_s  : std_logic_vector(1 downto 0);
  66
  67 begin
  68
  69         -- IRC for first axis
  70         irc1: irc_register
  71         port map
  72         (
  73                 clk_i    => clk_i,
  74                 reset_i  => reset_i,
  75                 a0_i     => irc1_a_i,
  76                 b0_i     => irc1_b_i,
  77                 index0_i => irc1_index_i,
  78                 mark0_i  => irc1_mark_i,
  79                 data_i   => data_i,
  80                 data_o   => irc1_out_s,
  81                 ce_i     => irc1_ce_s,
  82                 rd_i     => rd_i,
  83                 ta_o     => irc1_ta_s,
  84                 wr_i     => wr_i
  85         );
  86
  87         -- IRC for second axis
  88         irc2: irc_register
  89         port map
  90         (
  91                 clk_i    => clk_i,
  92                 reset_i  => reset_i,
  93                 a0_i     => irc2_a_i,
  94                 b0_i     => irc2_b_i,
  95                 index0_i => irc2_index_i,
  96                 mark0_i  => irc2_mark_i,
  97                 data_i   => data_i,
  98                 data_o   => irc2_out_s,
  99                 ce_i     => irc2_ce_s,
 100                 rd_i     => rd_i,
 101                 ta_o     => irc2_ta_s,
 102                 wr_i     => wr_i
 103         );
 104
 105         -- IRC for thrid axis
 106         irc3: irc_register
 107         port map
 108         (
 109                 clk_i    => clk_i,
 110                 reset_i  => reset_i,
 111                 a0_i     => irc3_a_i,
 112                 b0_i     => irc3_b_i,
 113                 index0_i => irc3_index_i,
 114                 mark0_i  => irc3_mark_i,
 115                 data_i   => data_i,
 116                 data_o   => irc3_out_s,
 117                 ce_i     => irc3_ce_s,
 118                 rd_i     => rd_i,
 119                 ta_o     => irc3_ta_s,
 120                 wr_i     => wr_i
 121         );
 122
 123         -- IRC for fourth axis
 124         irc4: irc_register
 125         port map
 126         (
 127                 clk_i    => clk_i,
 128                 reset_i  => reset_i,
 129                 a0_i     => irc4_a_i,
 130                 b0_i     => irc4_b_i,
 131                 index0_i => irc4_index_i,
 132                 mark0_i  => irc4_mark_i,
 133                 data_i   => data_i,
 134                 data_o   => irc4_out_s,
 135                 ce_i     => irc4_ce_s,
 136                 rd_i     => rd_i,
 137                 ta_o     => irc4_ta_s,
 138                 wr_i     => wr_i
 139         );
 140
 141         -- Bus update
 142         memory_bus_update: process(ce_i, address_i, irc1_out_s, irc1_ta_s, irc2_out_s, irc2_ta_s,
 143                                    irc3_out_s, irc3_ta_s, irc4_out_s, irc4_ta_s)
 144         begin
 145
 146                 -- Reset signals
 147                 -- 11 is the inactive address here
 148                 irc1_ce_s <= "11";
 149                 irc2_ce_s <= "11";
 150                 irc3_ce_s <= "11";
 151                 irc4_ce_s <= "11";
 152
 153                 ta_o      <= '0';
 154                 data_o    <= (others => 'X');
 155
 156                 if ce_i = '1' then
 157
 158                         -- We have 4-bit address, and IRC module has 3 registers
 159                         -- Higher bits choose which IRC module, lower bits are for registers of the module
 160                         case address_i(3 downto 2) is
 161                                 when "00" =>
 162                                         irc1_ce_s <= address_i(1 downto 0);
 163                                         data_o    <= irc1_out_s;
 164                                         ta_o      <= irc1_ta_s;
 165
 166                                 when "01" =>
 167                                         irc2_ce_s <= address_i(1 downto 0);
 168                                         data_o    <= irc2_out_s;
 169                                         ta_o      <= irc2_ta_s;
 170
 171                                 when "10" =>
 172                                         irc3_ce_s <= address_i(1 downto 0);
 173                                         data_o    <= irc3_out_s;
 174                                         ta_o      <= irc3_ta_s;
 175
 176                                 when "11" =>
 177                                         irc4_ce_s <= address_i(1 downto 0);
 178                                         data_o    <= irc4_out_s;
 179                                         ta_o      <= irc4_ta_s;
 180
 181                                 when others =>
 182                                         NULL;
 183
 184                         end case;
 185                 end if;
 186
 187         end process;
 188
 189 end Behavioral;