hw/clockgen.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 use work.lx_dad_pkg.all;
   6
   7 entity clockgen is
   8         port
   9         (
  10                 -- inputs
  11                 clk_i   : in std_logic;
  12                 reset_i : in std_logic;
  13                 sck_i   : in std_logic;
  14                 SDI             : in std_logic;
  15                 -- outputs
  16                 phi_1   : out std_logic;
  17                 phi_2   : out std_logic;
  18                 phi_st  : out std_logic;
  19                 ph_rst  : out std_logic;
  20         --      LED             : out std_logic;
  21                 sck_o   : out std_logic;
  22                 cnv_o   : out std_logic;
  23
  24
  25                 mem_o           : out std_logic_vector(31 downto 0);
  26
  27                 --memory related outputs
  28                 addr_o  : out std_logic_vector(10 downto 0);
  29                 bls_o   : out std_logic_vector(3 downto 0);
  30                 ce_o    : out std_logic;
  31
  32                 -- mem related inputs
  33
  34                 addr_i  : in std_logic_vector(3 downto 0);
  35                 data_i  : in std_logic_vector(31 downto 0);
  36                 ce_i    : in std_logic;
  37                 bls_i   : in std_logic_vector(3 downto 0);
  38                 data_o  : out std_logic_vector(31 downto 0)
  39
  40         );
  41 end clockgen;
  42
  43 architecture rtl of clockgen is
  44
  45         --constant CLK_MASTER_FREQ: unsigned := 50000000;
  46
  47         constant pixel_max: integer := 2047;
  48
  49         signal cntra    : unsigned(31 downto 0) := (others => '0');
  50         signal pixel            : integer range 0 to pixel_max;
  51         signal spd_cntr : integer range 0 to 3;
  52         signal spd_timer : integer range 0 to 255;
  53
  54         signal cntrb    : unsigned(31 downto 0) := (others => '0');
  55
  56         signal bank             : std_logic;
  57
  58         signal run_readout      : std_logic;
  59         signal conv_start       : std_logic;
  60         signal adc_data_i       : std_logic_vector(17 downto 0);
  61         signal adc_drdy_i       : std_logic;
  62         signal run_single       : std_logic;
  63         signal run_single_last : std_logic;
  64         signal run_single_i     : std_logic;
  65         signal finished         : std_logic:='0';
  66         signal finished_i       : std_logic:='0';
  67         signal stability_m      : std_logic;
  68
  69         type    states_i        is (i0, i1, i2, i3, i4, i5, i6, i7, i8, iddle);
  70         signal  state_i         : states_i;
  71
  72         type    meas_states is (normal, multi_per_pixel, leakage);
  73         signal state_meas       : meas_states;
  74
  75         signal  t1              : unsigned(31 downto 0);
  76         signal  t2              : unsigned(31 downto 0);
  77         signal  t3              : unsigned(31 downto 0);
  78         signal  t4              : unsigned(31 downto 0);
  79         signal  t5              : unsigned(31 downto 0);
  80         signal  t6              : unsigned(31 downto 0);
  81         signal  t7              : unsigned(31 downto 0);
  82         signal  t8              : unsigned(31 downto 0);
  83         signal  t9              : unsigned(31 downto 0) ;
  84         signal  pixel_last      : integer range 0 to pixel_max;
  85         signal  pixel_cnt       : integer range 0 to pixel_max;
  86         signal  pixel_addr      : integer range 0 to pixel_max;
  87
  88         signal  store_samples_s : std_logic;
  89         signal  sync_multi_s    : std_logic;
  90
  91         signal alive_cntr : integer range 0 to 24999999:=0;
  92         signal LED_latch  : std_logic:='1';
  93
  94 begin
  95
  96         snsor_adc_interface:lx_adc_if
  97         generic map
  98         (
  99                 adc_res         => 18,
 100                 conv_cycles     => 85
 101         )
 102         port map
 103         (
 104                 clk_i           => clk_i,
 105                 rst_i           => reset_i,
 106                 conv_start      => conv_start,
 107                 sck_o           => sck_o,
 108                 cnv_o           => cnv_o,
 109                 data_o          => adc_data_i,
 110                 drdy_o          => adc_drdy_i,
 111                 sck_i           => sck_i,
 112                 SDI                     => sdi
 113         );
 114
 115         -- adc_read : process(reset_i,clk_i)
 116         -- begin
 117                 -- if reset_i = '1' then
 118                 -- elsif rising_edge(clk_i) then
 119                         -- if adc_drdy_i = '1' and pixel < 1025 then
 120                                 --mem_o <= std_logic_vector(resize(unsigned(adc_data_i), mem_o'length));
 121                                 -- mem_o <= std_logic_vector(to_unsigned((pixel),32));
 122                                 -- addr_o <= bank & std_logic_vector(to_unsigned((pixel),10));
 123                                 -- bls_o <= "1111";
 124                                 -- ce_o <= '1';
 125                         -- end if;
 126                 -- end if;
 127         -- end process;
 128
 129         interf : process(reset_i,clk_i)
 130         begin
 131                 if reset_i = '1' then                   -- set default timing
 132                         t1 <= "00000000000000000000000000000110";       --6
 133                         t2 <= "00000000000000000000001111101000";       --9
 134                         t3 <= "00000000000000000000010001111101";       --1149
 135                         t4 <= "00000000000000000000001111101000";       --14
 136                         t5 <= "00000000000000000000000000000110";       --6
 137                         t6 <= "00000000000000000000001001010111";       --599
 138                         t7 <= "00000000000000000000001010010010";       --658
 139                         t8 <= "00000000000000000001001100010000";       --4880
 140                         t9 <= "00000000000000000000000111110011";
 141                         pixel_last <= 1023;
 142                         data_o <= (others => '0');
 143                         run_single <= '0';
 144                         run_readout <= '0';
 145                 elsif rising_edge(clk_i) then
 146                         run_single <= '0';
 147                         if finished = '1' then
 148                                 run_readout <= '0';
 149                                 finished_i <= '1';
 150                         end if;
 151                         if ce_i = '1' and bls_i /= "0000" then
 152                                 if addr_i = "0000" then
 153                                         run_readout <= data_i(0);       --start/stop the readout
 154                                         if data_i(1) = '1'  then
 155                                                 run_readout <= '1';
 156                                                 run_single <= '1';
 157                                         end if;
 158                                         if data_i(3) = '1' then
 159                                                 state_meas <= normal;
 160                                         elsif data_i(4) = '1' then
 161                                                 state_meas <= leakage;
 162                                         elsif data_i(5) = '1' then
 163                                                 state_meas <= multi_per_pixel;
 164                                         end if;
 165                                 elsif addr_i = "0001" then
 166                                         t1 <= unsigned(data_i);
 167                                 elsif addr_i = "0010" then
 168                                         t2 <= unsigned(data_i);
 169                                 elsif addr_i = "0011" then
 170                                         t3 <= unsigned(data_i);
 171                                 elsif addr_i = "0100" then
 172                                         t4 <= unsigned(data_i);
 173                                 elsif addr_i = "0101" then
 174                                         t5 <= unsigned(data_i);
 175                                 elsif addr_i = "0110" then
 176                                         t6 <= unsigned(data_i);
 177                                 elsif addr_i <= "0111" then
 178                                         t7 <= unsigned(data_i);
 179                                 elsif addr_i <= "1000" then
 180                                         t8 <= unsigned(data_i);
 181                                 elsif addr_i <= "1001" then
 182                                         t9 <= unsigned(data_i);
 183                                 elsif addr_i <= "1100" then
 184                                         pixel_last <= to_integer(unsigned(data_i));
 185                                 end if;
 186                         end if;
 187                         if ce_i = '1' then
 188                                 if addr_i = "0000" then
 189                                         data_o <= (others => '0');
 190                                         data_o(2) <= not bank;
 191                                         data_o(6) <= finished_i;
 192                                         data_o(0) <= run_readout;
 193                                         if state_meas = leakage then
 194                                                 data_o(4) <= '1';
 195                                         elsif state_meas = normal then
 196                                                 data_o(3) <= '1';
 197                                         elsif state_meas = multi_per_pixel then
 198                                                 data_o(5) <= '1';
 199                                         end if;
 200                                         finished_i <= '0';
 201                                 elsif addr_i = "0001" then
 202                                         data_o <= std_logic_vector(t1);
 203                                 elsif addr_i = "0010" then
 204                                         data_o <= std_logic_vector(t2);
 205                                 elsif addr_i = "0011" then
 206                                         data_o <= std_logic_vector(t3);
 207                                 elsif addr_i = "0100" then
 208                                         data_o <= std_logic_vector(t4);
 209                                 elsif addr_i = "0101" then
 210                                         data_o <= std_logic_vector(t5);
 211                                 elsif addr_i = "0110" then
 212                                         data_o <= std_logic_vector(t6);
 213                                 elsif addr_i = "0111" then
 214                                         data_o <= std_logic_vector(t7);
 215                                 elsif addr_i = "1000" then
 216                                         data_o <= std_logic_vector(t8);
 217                                 elsif addr_i = "1001" then
 218                                         data_o <= std_logic_vector(t9);
 219                                 elsif addr_i = "1100" then
 220                                         data_o <= std_logic_vector(to_unsigned(pixel_last, 32));
 221                                 else
 222                                         data_o <= "00000000000000000000000000000000";
 223                                 end if;
 224                         end if;
 225                 end if;
 226         end process;
 227
 228
 229         proc : process(clk_i, reset_i)
 230         begin
 231                 if reset_i='1' then
 232                         state_i <= iddle;
 233                         cntra <= (others => '0');
 234                         pixel <= 0;
 235                         phi_st <= '0';
 236                         bank <= '0';
 237                         ce_o <= '0';
 238                         bls_o <= "0000";
 239                         spd_cntr <= 3;
 240                         pixel_cnt <= 1023;
 241                         pixel_addr <= 0;
 242                         conv_start <= '0';
 243                         store_samples_s <= '0';
 244                         sync_multi_s <= '0';
 245                 elsif rising_edge(clk_i) then
 246                         ce_o <= '0';
 247                         bls_o <= "0000";
 248                         conv_start <= '0';
 249                         sync_multi_s <= '0';
 250                         finished <= '0';
 251                         if run_single = '1' then
 252                                 run_single_i <= '1';
 253                         end if;
 254                         if run_readout = '1' then
 255                                 cntrb <= cntrb + 1;
 256                         else
 257                                 cntrb <= (others => '0');
 258                         end if;
 259
 260                         if (state_meas = multi_per_pixel) and (store_samples_s = '1') then
 261                                 if sync_multi_s = '1' then
 262                                         spd_timer <= 125 - 1;
 263                                 else
 264                                         if spd_timer > 0 then
 265                                                 spd_timer <= spd_timer - 1;
 266                                         else
 267                                                 spd_timer <= 125 - 1;
 268                                                 conv_start <= '1';
 269                                         end if;
 270                                 end if;
 271                         end if;
 272
 273                         if adc_drdy_i = '1' and store_samples_s = '1' then
 274                                 mem_o <= "00000000000000" & adc_data_i;
 275                                 addr_o <= bank & std_logic_vector(to_unsigned((pixel_addr),addr_o'length -1));
 276                                 bls_o <= "1111";
 277                                 ce_o <= '1';
 278                                 if pixel_addr /= (2 ** (addr_o'length - 1)) - 1  then
 279                                         pixel_addr <= pixel_addr + 1;
 280                                 else
 281                                         store_samples_s <= '0';
 282                                 end if;
 283                         end if;
 284
 285                         if cntra = 0 then
 286                                 case state_meas is
 287                                 when leakage =>
 288                                         case state_i is
 289                                         when i0 =>
 290                                                 if pixel > 1023 then
 291                                                         bank <= not bank;
 292                                                         state_i <= iddle;
 293                                                         if run_single_i = '1' and run_single_last = '0' then
 294                                                                 run_single_last <= '1';
 295                                                         end if;
 296                                                         if run_single_i = '1' and run_single_last = '1' then
 297                                                                 run_single_i <= '0';
 298                                                                 run_single_last <= '0';
 299                                                                 finished <= '1';
 300                                                         end if;
 301                                                         pixel_addr <= 0;
 302                                                         store_samples_s <= '1';
 303                                                 end if;
 304                                                 pixel <= pixel +1;
 305                                                 conv_start <= '1';
 306                                                 cntra <= t9;
 307                                         when others =>
 308                                                 pixel <= 0;
 309                                                 cntra <= (others => '0');
 310                                                 ph_rst <= '0';
 311                                                 if  cntrb > t8 then
 312                                                         state_i <= i0;
 313                                                         cntra <= t9;
 314                                                         cntrb <= (others => '0');
 315                                                         ph_rst <= '1';
 316                                                 end if;
 317                                         end case;
 318                                 when normal | multi_per_pixel =>
 319                                         case state_i is
 320                                         when i0 =>
 321                                                 state_i <= i1;
 322                                                 cntra<=t1;
 323                                                 phi_2 <= '0';
 324                                         when i1 =>
 325                                                 state_i <= i2;
 326                                                 phi_1 <= '1';
 327                                                 cntra<=t2;
 328                                         when i2 =>
 329                                                 state_i <= i3;
 330                                                 ph_rst <= '0';
 331                                                 cntra<=t3;
 332                                         when i3 =>
 333                                                 ph_rst <= '1';
 334                                                 phi_st <= '0';
 335                                                 state_i <= i4;
 336                                                 cntra<=t4;
 337                                         when i4 =>
 338                                                 phi_1 <= '0';
 339                                                 if pixel_cnt = 0 then
 340                                                         bank <= not bank;
 341                                                         state_i <= iddle;
 342                                                         cntra <= (others => '0');
 343                                                         if run_single_i = '1' and run_single_last = '0' then
 344                                                                 run_single_last <= '1';
 345                                                         end if;
 346                                                         if run_single_i = '1' and run_single_last = '1' then
 347                                                                 run_single_i <= '0';
 348                                                                 run_single_last <= '0';
 349                                                                 finished <= '1';
 350                                                         end if;
 351                                                 else
 352                                                         pixel_cnt <= pixel_cnt - 1;
 353                                                         state_i <= i5;
 354                                                         cntra<=t5;
 355                                                 end if;
 356                                         when i5 =>
 357                                                 phi_2 <= '1';
 358                                                 state_i <= i6;
 359                                                 cntra <= t6;
 360                                         when i6 =>
 361                                                 state_i <= i0;
 362                                                 -- start the readout from adc
 363                                                 cntra <= t7;
 364                                                 if run_readout = '1' then
 365                                                         if pixel > 0 then
 366                                                                 if state_meas = normal then
 367                                                                         conv_start <= '1';
 368                                                                 else
 369                                                                         sync_multi_s <= '1';
 370                                                                 end if;
 371                                                         end if;
 372                                                         if pixel = 0 then
 373                                                                 pixel_addr <= 0;
 374                                                                 store_samples_s <= '1';
 375                                                                 phi_st <= '1';
 376                                                         end if;
 377                                                 end if;
 378                                                 pixel <= pixel + 1;
 379                                         when others =>
 380                                                 if cntrb > t8 then
 381                                                         cntrb <= (others => '0');
 382                                                         state_i <= i1;
 383                                                 end if;
 384                                                 pixel <= 0;
 385                                                 phi_1 <= '0';
 386                                                 phi_2 <= '0';
 387                                                 ph_rst <= '0';
 388                                                 cntra <= (others => '0');
 389                                                 pixel_cnt <= pixel_last;
 390                                         end case;
 391                                 when others =>
 392                                         pixel_cnt <= 0;
 393                                 end case;
 394                         else
 395                                 cntra <= cntra - 1;
 396                         end if;
 397                 end if;
 398         end process;
 399
 400         alive : process(clk_i,reset_i)
 401         begin
 402                 if reset_i = '1' then
 403                         alive_cntr <= 0;
 404                         --LED <= '1';
 405                         LED_latch<= '1';
 406                 elsif rising_edge(clk_i) then
 407                         alive_cntr<=alive_cntr+1;
 408                         if alive_cntr = 24999999 then
 409                                 LED_latch <= not LED_latch;
 410                         --      LED <= LED_latch;
 411                                 alive_cntr<=0;
 412                         end if;
 413                 end if;
 414         end process;
 415 end architecture;