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Include hardware design of FPGA peripherals to external LPC bus connection.
[fpga/lx-cpu1/lx-dad.git] / hw / cnt_div.vhd
1 --
2 -- * Counter - divider *
3 --
4 -- part of LXPWR motion control board (c) PiKRON Ltd
5 -- idea by Pavel Pisa PiKRON Ltd <ppisa@pikron.com>
6 --
7 -- license: BSD
8 --
9
10 library ieee;
11 use ieee.std_logic_1164.all;
12 use ieee.numeric_std.all;
13
14 entity cnt_div is
15         generic (
16                 cnt_width_g : natural := 8
17         );
18         port
19         (
20                 clk_i     : in std_logic;
21                 en_i      : in std_logic;
22                 reset_i   : in std_logic;
23                 ratio_i   : in std_logic_vector(cnt_width_g-1 downto 0);
24                 q_out_o   : out std_logic
25         );
26 end cnt_div;
27
28 architecture behavioral of cnt_div is
29         signal cnt_val_s : natural range 0 to (2**cnt_width_g - 1);
30         signal cnt_val_r : natural range 0 to (2**cnt_width_g - 1);
31 begin
32
33 comb: process (reset_i, en_i, ratio_i, cnt_val_r)
34         begin
35                 if reset_i = '1' then
36                         cnt_val_s <= to_integer(unsigned(ratio_i));
37                         q_out_o   <= '0';
38                 else
39                         if en_i = '0' then
40                                 cnt_val_s <= cnt_val_r;
41                                 q_out_o   <= '0';
42                         else
43                                 if cnt_val_r <= 1 then
44                                         cnt_val_s <= to_integer(unsigned(ratio_i));
45                                         q_out_o   <= '1';
46                                 else
47                                         cnt_val_s <= cnt_val_r - 1;
48                                         q_out_o   <= '0';
49                                 end if;
50                         end if;
51                 end if;
52         end process;
53
54 seq: process
55         begin
56                 wait until clk_i'event and clk_i = '1';
57                 cnt_val_r <= cnt_val_s;
58         end process;
59
60 end behavioral;