PPC: Sleep mode and wakeup pin now working

diff --git a/arch/arm/arm_cm3/drivers/Mcu.c b/arch/arm/arm_cm3/drivers/Mcu.c
index 075ed34cf1d6879ca954962c630ee8b305125053..17b391f99101b46508517f8a1117c8b98e536359 100644 (file)
--- a/arch/arm/arm_cm3/drivers/Mcu.c
+++ b/arch/arm/arm_cm3/drivers/Mcu.c
@@ -497,7 +497,6 @@ void Mcu_SetMode(const Mcu_ModeType McuMode)
   //VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );\r
   (void) McuMode;\r
 \r
-  /* NOT SUPPORTED */\r
 }\r
 \r
 //-------------------------------------------------------------------\r

diff --git a/arch/ppc/mpc55xx/drivers/Mcu.c b/arch/ppc/mpc55xx/drivers/Mcu.c
index 350f918339e02b5bc7983a8546ee98c0431c3a76..dae6e09fa925f8839a64d7466a642e83fdbdef18 100644 (file)
--- a/arch/ppc/mpc55xx/drivers/Mcu.c
+++ b/arch/ppc/mpc55xx/drivers/Mcu.c
@@ -666,7 +666,10 @@ void Mcu_PerformReset(void)
 \r
 /**\r
  *\r
- *\r
+ * Application Notes!\r
+ * - AN3584, "MPC5510 Family Low Power Features"\r
+ *   Since it's not complete also check MPC5668\r
+ * - AN4150 , "Using Sleep Mode on the MPC5668x" and it's code\r
  *\r
  *\r
  * @param LPM\r
@@ -710,6 +713,9 @@ static void enterLowPower (Mcu_ModeType mcuMode )
         *   although the code does not take that much space.\r
         * */\r
        McuE_EnterLowPower(mcuMode);\r
+\r
+    /* Clear sleep flags to allow pads to operate */\r
+    CRP.PSCR.B.SLEEPF = 0x1;\r
 }\r
 \r
 \r

diff --git a/arch/ppc/mpc55xx/drivers/Mcu_Sleep.sx b/arch/ppc/mpc55xx/drivers/Mcu_Sleep.sx
index 8784f78c4d1c751d00ef130c4baccd79c0cb8ad5..aa6cb3f4e3294f80a77ee612f014f43dadc40eb7 100644 (file)
--- a/arch/ppc/mpc55xx/drivers/Mcu_Sleep.sx
+++ b/arch/ppc/mpc55xx/drivers/Mcu_Sleep.sx
@@ -12,7 +12,7 @@
 #endif\r
 \r
 \r
-#define CRP_RECPTR             0xfffe0058\r
+#define CRP_RECPTR             0xfffec058\r
 \r
        .global McuE_EnterLowPower\r
        \r
@@ -27,7 +27,7 @@ McuE_EnterLowPower:
        mfXER   r30\r
        mfCTR   r31\r
        stmw    r25, 0x78(r1)   #-- Store SPR data to stack\r
-       \r
+               \r
        LOAD_ADDR_32(r4,CRP_RECPTR)\r
        stw             r1,0x0(r4)      //  Save stack pointer to CRP to be preserved during LPM\r
        .long   0x7C00007C      //  Wait instruction\r
@@ -72,34 +72,30 @@ McuE_LowPowerVector:
        .global McuE_LowPowerRecoverFlash\r
 \r
 /*\r
- * When we come back here only TLB0 is setup.\r
- * - Map up the entire flash \r
+ * When we come back here only TLB0 is setup for flash and then only 4K\r
  */    \r
 McuE_LowPowerRecoverFlash:\r
-       LOAD_ADDR_32(5,0x10030000)\r
-    mtspr SPR_MAS0,r5     \r
-    LOAD_ADDR_32(5,0xC0000500)\r
-    mtspr SPR_MAS1,r5     \r
-    LOAD_ADDR_32(5,0x40000008)\r
-    mtspr SPR_MAS2,r5     \r
-    LOAD_ADDR_32(5,0x4000003F)\r
-    mtspr SPR_MAS3,r5\r
-    tlbwe\r
-\r
-    LOAD_ADDR_32(r3,0xfffe8600+52)\r
-       stb             1,0(r3) \r
     \r
+    bl cfg_MMU\r
+ \r
+ \r
+#if 0 \r
+       // Setup the SIU again.\r
+       li       r4,0x0202\r
+    LOAD_ADDR_32(r3,0xfffe8040+(52*2))         // PD4, SIU_PCR \r
+       sth  r4,0(r3)\r
+       \r
+       LOAD_ADDR_32(r3,0xfffe8600+52)          // PD4, SIU_GPDO\r
+       stb             1,0(r3) \r
+\r
     // Release PAD keepers\r
-    LOAD_ADDR_32(r3,0xfffec060)\r
+    LOAD_ADDR_32(r3,0xfffec060)   // CRP_PSCR\r
     LOAD_ADDR_32(r4,0x1000)\r
     stw         r4,0(r3)\r
-           \r
-apa:    \r
-    b  apa\r
+#endif    \r
     \r
 /* Recover the stack */\r
-    lis        r4,0xFFFE\r
-       ori     r4,r4,0xC058    #-- CRP.RECPRTR address\r
+       LOAD_ADDR_32(r4,CRP_RECPTR)\r
        lwz     r1,0x0(r4)      #-- Restore stack pointer from CRP\r
        lmw     r25,0x78(r1)    #-- Load SPR values back into GPRs\r
        mtSRR1  r25\r
@@ -116,5 +112,71 @@ apa:
     /* branch back to Mcu_SetMode().. */\r
     blr\r
  \r
+ \r
+ #if defined(CFG_VLE)\r
+ #define VLE_VAL               MAS2_VLE\r
+ #else\r
+ #define VLE_VAL               0\r
+ #endif\r
+\r
+#define SRAM_START                     0x40000000\r
+#define FLASH_START                    0x00000000\r
+#define PERIPHERAL_START       0xfff00000\r
+\r
+ \r
+ cfg_MMU:\r
+\r
+#***************************************************/\r
+#     setup MMU                                    */\r
+#***************************************************/\r
+\r
+#TLB Entry 0 =  1M Internal flash \r
+       LOAD_ADDR_32(5, 0x10000000 + (0<<16))\r
+    mtspr SPR_MAS0,r5     \r
+    LOAD_ADDR_32(5, 0xC0000000 + MAS1_TSIZE_4M )\r
+    mtspr SPR_MAS1,r5     \r
+    LOAD_ADDR_32(5, FLASH_START + VLE_VAL )\r
+    mtspr SPR_MAS2,r5     \r
+    LOAD_ADDR_32(5, FLASH_START + MAS3_FULL_ACCESS )\r
+    mtspr SPR_MAS3,r5\r
+    msync\r
+    isync\r
+       tlbwe\r
+       isync\r
+\r
+\r
+#TLB Entry 1 =  Peripheral bridge and BAM\r
+       LOAD_ADDR_32(5, 0x10000000 + (1<<16))\r
+    mtspr SPR_MAS0,r5     \r
+    LOAD_ADDR_32(5, 0xC0000000 + MAS1_TSIZE_1M)\r
+    mtspr SPR_MAS1,r5\r
+    LOAD_ADDR_32(5, PERIPHERAL_START + VLE_VAL +  MAS2_I)\r
+    mtspr SPR_MAS2,r5     \r
+    LOAD_ADDR_32(5, PERIPHERAL_START + MAS3_FULL_ACCESS )\r
+    mtspr SPR_MAS3,r5\r
+    msync\r
+    isync\r
+       tlbwe\r
+       isync\r
+\r
+\r
+#TLB Entry 2 =  External RAM. Skip this. \r
+\r
+#TLB Entry 3 =  Internal SRAM\r
+       LOAD_ADDR_32(5, 0x10000000+(3<<16))\r
+    mtspr SPR_MAS0,r5     \r
+    LOAD_ADDR_32(5, 0xC0000000 + MAS1_TSIZE_256K )\r
+    mtspr SPR_MAS1,r5     \r
+    LOAD_ADDR_32(5, SRAM_START + VLE_VAL )\r
+    mtspr SPR_MAS2,r5     \r
+    LOAD_ADDR_32(5, SRAM_START + MAS3_FULL_ACCESS )\r
+    mtspr SPR_MAS3,r5\r
+    msync\r
+    isync\r
+       tlbwe\r
+       isync\r
+       blr\r
+       \r
+ \r
 \r
 \r

diff --git a/include/ppc/asm_ppc.h b/include/ppc/asm_ppc.h
index 54cb6747f94e61970e5c062927f2c7c9d966e085..cd434b788c2f943de1085458288efa711291685b 100644 (file)
--- a/include/ppc/asm_ppc.h
+++ b/include/ppc/asm_ppc.h
@@ -75,6 +75,34 @@
 \r
 #define INTC_SSCIR7 0xFFF48027\r
 \r
+/* MAS bits */\r
+#define MAS1_TSIZE_4K                  (1<<8)\r
+#define MAS1_TSIZE_16K                 (2<<8)\r
+#define MAS1_TSIZE_64K                 (3<<8)\r
+#define MAS1_TSIZE_256K                        (4<<8)\r
+#define MAS1_TSIZE_1M                  (5<<8)\r
+#define MAS1_TSIZE_4M                  (6<<8)\r
+#define MAS1_TSIZE_16M                 (7<<8)\r
+#define MAS1_TSIZE_64M                 (8<<8)\r
+#define MAS1_TSIZE_256M                        (8<<9)\r
+\r
+#define MAS2_VLE       (1<<5)\r
+#define MAS2_W         (1<<4)\r
+#define MAS2_I         (1<<3)\r
+#define MAS2_M         (1<<2)\r
+#define MAS2_G         (1<<1)\r
+#define MAS2_E         (1<<0)\r
+\r
+#define MAS3_UX                (1<<5)\r
+#define MAS3_SX                (1<<4)\r
+#define MAS3_UW                (1<<3)\r
+#define MAS3_SW                (1<<2)\r
+#define MAS3_UR                (1<<1)\r
+#define MAS3_SR                (1<<0)\r
+\r
+#define MAS3_FULL_ACCESS (MAS3_UX+MAS3_UW+MAS3_UR+MAS3_SX+MAS3_SW+MAS3_SR)\r
+\r
+\r
 #if defined(_ASSEMBLER_)\r
 /*\r
  * PPC vs VLE assembler:\r