-\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Include Files */\r
-\r
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
#include "Can.h"\r
#include "Dem.h"\r
#endif\r
#include "Det.h"\r
-//#include "Spi.h"\r
-//#include "EcuM_Cbk.h"\r
#include "CanIf_Cbk.h"\r
-//#include "MemMap.h"\r
#include "Os.h"\r
#include "irq.h"\r
+#include "Mcu.h"\r
+\r
+#define DCAN1_MAX_MESSAGEBOXES 64\r
+#define DCAN2_MAX_MESSAGEBOXES 64\r
+#define DCAN3_MAX_MESSAGEBOXES 32\r
\r
+#define CAN_TIMEOUT_DURATION 0xFFFFFFFF\r
+#define CAN_INSTANCE 0\r
\r
\r
#if !defined(USE_DEM)\r
/*----------------------------------------------------------------------------*/\r
/* Variable Definition */\r
\r
+// Array for easy access to DCAN register definitions.\r
static Can_RegisterType* CanBase[]=\r
{\r
- Can0_Base,\r
-#ifdef Can1_Base\r
- Can1_Base\r
-#endif\r
+ DCAN1_Base,\r
+ DCAN2_Base,\r
+ DCAN3_Base\r
};\r
\r
typedef enum\r
CAN_READY\r
} Can_StateType;\r
\r
-typedef enum\r
-{\r
- INTERRUPT = 0x00000400,\r
- POLLING = 0x00000000\r
-} OpMode;\r
\r
typedef struct\r
{\r
- OpMode BusOff;\r
- OpMode RxProc;\r
- OpMode TxProc;\r
- OpMode WakeupProc;\r
- uint16 MessageBoxCount;\r
uint16 MaxBoxes;\r
- uint8 FirstHandle;\r
uint32 WakeupSrc;\r
- uint32 *MaskRefPtr;\r
Can_PduType *PduPtr;\r
uint8 *CancelPtr;\r
uint8 *TxPtr; \r
/* Module is in uninitialized state */\r
static Can_StateType ModuleState = CAN_UNINIT;\r
#endif\r
-static CanIf_ControllerModeType ControllerMode[CAN_CONTROLLER_COUNT];\r
+\r
+static CanIf_ControllerModeType ControllerMode[CAN_ARC_CTRL_CONFIG_CNT];\r
\r
/* Used to switch between IF1 and IF2 of DCAN */\r
static uint8 IfRegId = 0;\r
static const Can_ConfigType *CurConfig;\r
\r
/* To save the PduData of transmission objects */\r
-static Can_PduType PduInfoArray_0[MAX_MESSAGEBOXES_0];\r
+static Can_PduType PduInfoArray_1[DCAN1_MAX_MESSAGEBOXES];\r
/* To save pending Cancel Requests of transmission objects */\r
-static uint8 CancelRqstArray_0[MAX_MESSAGEBOXES_0];\r
+static uint8 CancelRqstArray_1[DCAN1_MAX_MESSAGEBOXES];\r
/* To save pending Transmit Requests of transmission objects */\r
-static uint8 TxRqstArray_0[MAX_MESSAGEBOXES_0];\r
-/* Array to save Filtermask references of MessageObjects */\r
-static uint32 FilterMaskRef_0[MESSAGEBOX_COUNT_0];\r
-\r
-#ifdef CanController_1\r
-static Can_PduType PduInfoArray_1[MAX_MESSAGEBOXES_1];\r
-static uint8 CancelRqstArray_1[MAX_MESSAGEBOXES_1];\r
-static uint8 TxRqstArray_1[MAX_MESSAGEBOXES_1];\r
-static uint32 FilterMaskRef_1[MESSAGEBOX_COUNT_1];\r
-#endif\r
+static uint8 TxRqstArray_1[DCAN1_MAX_MESSAGEBOXES];\r
+\r
+static Can_PduType PduInfoArray_2[DCAN2_MAX_MESSAGEBOXES];\r
+static uint8 CancelRqstArray_2[DCAN2_MAX_MESSAGEBOXES];\r
+static uint8 TxRqstArray_2[DCAN2_MAX_MESSAGEBOXES];\r
+\r
+static Can_PduType PduInfoArray_3[DCAN3_MAX_MESSAGEBOXES];\r
+static uint8 CancelRqstArray_3[DCAN3_MAX_MESSAGEBOXES];\r
+static uint8 TxRqstArray_3[DCAN3_MAX_MESSAGEBOXES];\r
+\r
\r
/* Holds the Controller specific configuration */ \r
static Controller_PreConfigType ControllerConfig[] =\r
{\r
- {\r
- BUSOFF_PROCESSING_0,\r
- RX_PROCESSING_0,\r
- TX_PROCESSING_0,\r
- WAKEUP_PROCESSING_0,\r
- MESSAGEBOX_COUNT_0,\r
- MAX_MESSAGEBOXES_0,\r
- FIRST_HANDLE_0,\r
- WAKEUP_SRC_REF_0,\r
- FilterMaskRef_0,\r
- PduInfoArray_0,\r
- CancelRqstArray_0,\r
- TxRqstArray_0\r
+ { // DCAN1\r
+ .MaxBoxes = DCAN1_MAX_MESSAGEBOXES,\r
+ .WakeupSrc = 0,\r
+ .PduPtr = PduInfoArray_1,\r
+ .CancelPtr = CancelRqstArray_1,\r
+ .TxPtr = TxRqstArray_1\r
},\r
-#ifdef CanController_1\r
- {\r
- BUSOFF_PROCESSING_1,\r
- RX_PROCESSING_1,\r
- TX_PROCESSING_1,\r
- WAKEUP_PROCESSING_1,\r
- MESSAGEBOX_COUNT_1,\r
- MAX_MESSAGEBOXES_1,\r
- FIRST_HANDLE_1,\r
- WAKEUP_SRC_REF_1,\r
- FilterMaskRef_1,\r
- PduInfoArray_1,\r
- CancelRqstArray_1,\r
- TxRqstArray_1\r
- }\r
-#endif\r
+ { // DCAN2\r
+ .MaxBoxes = DCAN2_MAX_MESSAGEBOXES,\r
+ .WakeupSrc = 1,\r
+ .PduPtr = PduInfoArray_2,\r
+ .CancelPtr = CancelRqstArray_2,\r
+ .TxPtr = TxRqstArray_2\r
+ },\r
+ { // DCAN3\r
+ .MaxBoxes = DCAN3_MAX_MESSAGEBOXES,\r
+ .WakeupSrc = 1,\r
+ .PduPtr = PduInfoArray_3,\r
+ .CancelPtr = CancelRqstArray_3,\r
+ .TxPtr = TxRqstArray_3\r
+ }\r
+\r
};\r
\r
/* Shadow Buffer is used for buffering of received data */ \r
-static uint8 RxShadowBuf[8];\r
+static uint8 RxShadowBuf[CAN_ARC_CTRL_CONFIG_CNT][8];\r
\r
/* Driver must know how often Can_DisableControllerInterrupts() has been called */\r
-static uint32 IntDisableCount[CAN_CONTROLLER_COUNT];\r
+static uint32 IntDisableCount[CAN_ARC_CTRL_CONFIG_CNT];\r
+\r
+\r
+static inline const Can_HardwareObjectType * Can_FindTxHoh(Can_Arc_HTHType hth) {\r
+ for (int i = 0; i < CAN_ARC_CTRL_CONFIG_CNT; i++) {\r
+ const Can_HardwareObjectType * hoh = CanControllerConfigData[i].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT && hoh->CanObjectId == hth) {\r
+ return hoh;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ }\r
+ return 0;\r
+}\r
\r
+static inline uint8 Can_FindControllerId(Can_Arc_HTHType hth) {\r
+ for (int i = 0; i < CAN_ARC_CTRL_CONFIG_CNT; i++) {\r
+ const Can_HardwareObjectType * hoh = CanControllerConfigData[i].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT && hoh->CanObjectId == hth) {\r
+ return i;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ }\r
+ return 0;\r
+}\r
\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can1_InterruptHandler_0 */\r
-/* Description: CAN Node 1 Level 0 Interrupt Service Routine */\r
-/* Return Value: None */\r
-/* Remarks: -/- */\r
-/* */\r
+static inline const Can_HardwareObjectType * Can_FindRxHoh(CanControllerIdType Controller, uint8 msgNr) {\r
+ const Can_HardwareObjectType * hoh = CanControllerConfigData[Controller].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_RECEIVE\r
+ && (hoh->Can_Arc_MbMask & (1 << (msgNr - 1))) ) {\r
+ return hoh;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ return 0;\r
+}\r
\r
-//#pragma INTERRUPT(CAN1_INTERRUPTHANDLER_0,IRQ)\r
\r
-void CAN1_INTERRUPTHANDLER_0()\r
+void Can_InterruptHandler(CanControllerIdType controller)\r
{\r
uint32 ErrCounter;\r
uint32 MsgNr;\r
\r
ErrCounter = CAN_TIMEOUT_DURATION;\r
\r
- uint32 ir = CanBase[0]->IR;\r
+ uint32 ir = CanBase[controller]->IR;\r
\r
if(ir == 0x8000)\r
{\r
- uint32 sr = CanBase[0]->SR;\r
+ uint32 sr = CanBase[controller]->SR;\r
/* WakeUp Pending */\r
if(sr & 0x00000200) {\r
/* Set Init Bit, so that Controller is in Stop state */\r
- CanBase[0]->CTL |= 0x1;\r
+ CanBase[controller]->CTL |= 0x1;\r
// EcuM_CheckWakeUp(ControllerConfig[0].WakeupSrc);\r
\r
}\r
/* Bus Off */\r
if(sr & 0x00000080) {\r
- Can_SetControllerMode(0, CAN_T_STOP); // CANIF272\r
+ Can_SetControllerMode(controller, CAN_T_STOP); // CANIF272\r
//CanIf_ControllerBusOff(0); // Not implemented in Arctic Core\r
\r
}\r
MsgNr = ir;\r
\r
/* Read Arbitration, Control and Data Bits and clear IntPnd and NewDat*/\r
- CanBase[0]->IFx[IfRegId].COM = 0x003F0000 | MsgNr;\r
+ CanBase[controller]->IFx[IfRegId].COM = 0x003F0000 | MsgNr;\r
\r
/* Wait until Busy Flag is 0 */\r
- while(CanBase[0]->IFx[IfRegId].COM & 0x8000)\r
+ while(CanBase[controller]->IFx[IfRegId].COM & 0x8000)\r
{\r
ErrCounter--;\r
if(ErrCounter == 0)\r
}\r
\r
/* Transmit Object */\r
- if(CanBase[0]->IFx[IfRegId].ARB & 0x20000000)\r
+ if(CanBase[controller]->IFx[IfRegId].ARB & 0x20000000)\r
{\r
/* Reset TxRqst-Array Element */\r
- TxRqstArray_0[MsgNr - 1] = 0;\r
+ ControllerConfig[controller].TxPtr[MsgNr - 1] = 0;\r
/* A Message was successfully transmitted */\r
- CanIf_TxConfirmation(PduInfoArray_0[MsgNr - 1].swPduHandle);\r
+ CanIf_TxConfirmation(ControllerConfig[controller].PduPtr[MsgNr - 1].swPduHandle);\r
}\r
/* Receive Object */\r
else\r
{\r
/* Extended Id */\r
- if(CanBase[0]->IFx[IfRegId].ARB & 0x40000000)\r
+ if(CanBase[controller]->IFx[IfRegId].ARB & 0x40000000)\r
{\r
/* Bring Id to standardized format (MSB marks extended Id) */\r
- MsgId = (CanBase[0]->IFx[IfRegId].ARB & 0x1FFFFFFF) | 0x80000000;\r
+ MsgId = (CanBase[controller]->IFx[IfRegId].ARB & 0x1FFFFFFF) | 0x80000000;\r
}\r
/* Standard Id */\r
else\r
{\r
/* Bring Id to standardized format (MSB marks extended Id) */\r
- MsgId = (CanBase[0]->IFx[IfRegId].ARB & 0x1FFC0000) >> 18;\r
+ MsgId = (CanBase[controller]->IFx[IfRegId].ARB & 0x1FFC0000) >> 18;\r
}\r
/* DLC (Max 8) */\r
- MsgDlc = CanBase[0]->IFx[IfRegId].MC & 0x000F;\r
+ MsgDlc = CanBase[controller]->IFx[IfRegId].MC & 0x000F;\r
if(MsgDlc > 8)\r
{\r
MsgDlc = 8;\r
}\r
/* Let SduPtr point to Shadow Buffer */\r
- SduPtr = RxShadowBuf;\r
+ SduPtr = RxShadowBuf[controller];\r
\r
/* Copy Message Data to Shadow Buffer */\r
for(DataByteIndex = 0; DataByteIndex < MsgDlc; DataByteIndex++)\r
{\r
- RxShadowBuf[DataByteIndex] = CanBase[0]->IFx[IfRegId].DATx[ElementIndex[DataByteIndex]];\r
+ SduPtr[DataByteIndex] = CanBase[controller]->IFx[IfRegId].DATx[ElementIndex[DataByteIndex]];\r
}\r
/* Indicate successful Reception */\r
- CanIf_RxIndication(CurConfig->MessageBoxPtr[MsgNr - 1].ObjectId, MsgId, MsgDlc, SduPtr);\r
+ const Can_HardwareObjectType *hoh = Can_FindRxHoh(controller, MsgNr);\r
+ CanIf_RxIndication(hoh->CanObjectId, MsgId, MsgDlc, SduPtr);\r
+\r
}\r
}\r
//Can_EnableControllerInterrupts(0);\r
}\r
\r
+void Can1_InterruptHandler() {\r
+ Can_InterruptHandler(DCAN1);\r
+}\r
\r
+void Can2_InterruptHandler() {\r
+ Can_InterruptHandler(DCAN2);\r
+}\r
\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can_Init */\r
-/* Service Id: 0x00 */\r
-/* Execution: Synchronous */\r
-/* Re-entrant: No */\r
-/* Description: Initialize Can Driver */\r
-/* ConfigPtr: Pointer to initialization data */\r
-/* Return Value: None */\r
-/* Remarks: */\r
-/* */\r
-void CAN_INIT(const Can_ConfigType *Config)\r
+void Can3_InterruptHandler() {\r
+ Can_InterruptHandler(DCAN3);\r
+}\r
+\r
+uint32 Can_CalculateBTR(uint8 Controller) {\r
+\r
+ uint32 clock = McuE_GetPeripheralClock(PERIPHERAL_CLOCK_CAN);\r
+ uint32 tq1 = CanControllerConfigData[Controller].CanControllerPropSeg + CanControllerConfigData[Controller].CanControllerSeg1;\r
+ uint32 tq2 = CanControllerConfigData[Controller].CanControllerSeg2;\r
+ uint32 ntq = tq1 + tq2 + 1 + 1 + 1;\r
+ uint32 brp = clock / (CanControllerConfigData[Controller].CanControllerBaudRate * 1000 * ntq) - 1;\r
+\r
+ uint32 retVal = (brp | (tq1 << 8) | (tq2 << 12));\r
+ return retVal;\r
+}\r
+\r
+\r
+void Can_Init(const Can_ConfigType *Config)\r
{\r
uint32 Controller;\r
uint8 MsgNr;\r
uint32 ErrCounter;\r
- Can_ControllerConfigType *CurControllerPtr;\r
- Can_MessageObjectType *MsgBoxPtr;\r
- uint32 *CurFilterMaskPtr;\r
uint32 Eob;\r
\r
/* DET Error Check */\r
}\r
#endif \r
\r
+ // TODO This should be used instead of other variables in the Can_Lcfg file.\r
CurConfig = Config;\r
- /* Set Pointer to ControllerConfig */\r
- CurControllerPtr = Config->ControllerConfigPtr; \r
- /* Set Pointer to MessageObjects */\r
- MsgBoxPtr = CurConfig->MessageBoxPtr;\r
\r
- for(Controller = 0; Controller < CAN_CONTROLLER_COUNT; Controller++)\r
+ for(Controller = 0; Controller < CAN_ARC_CTRL_CONFIG_CNT; Controller++)\r
{\r
ErrCounter = CAN_TIMEOUT_DURATION;\r
\r
/* Init, IE, AutomaticRetransmission, ConfChangeEnable, ABO Off,Parity On, SIE and EIE depending on ControllerConfig */\r
#if(CAN_WAKEUP_SUPPORT == STD_ON)\r
- CanBase[Controller]->CTL = 0x02001643 | (ControllerConfig[Controller].WakeupProc >> 8) | (ControllerConfig[Controller].BusOff >> 7);\r
+ CanBase[Controller]->CTL = 0x02001643;// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8) | (CanControllerConfigData[Controller].CanBusOffProcessing >> 7);\r
#else\r
- CanBase[Controller]->CTL = 0x00001643 | (ControllerConfig[Controller].WakeupProc >> 8) | (ControllerConfig[Controller].BusOff >> 7);\r
+ CanBase[Controller]->CTL = 0x00001643;// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8) | (CanControllerConfigData[Controller].CanBusOffProcessing >> 7);\r
#endif \r
/* LEC 7, TxOk, RxOk, PER */\r
CanBase[Controller]->SR = 0x0000011F;\r
//CanBase[Controller]->CTL |= 0x00000080;\r
//CanBase[Controller]->TR = 0x00000018;\r
\r
- for(MsgNr = 0; MsgNr < ControllerConfig[Controller].MaxBoxes; MsgNr++)\r
- {\r
+\r
+ // Basic message object initialization\r
+ for(MsgNr = 0; MsgNr < ControllerConfig[Controller].MaxBoxes; MsgNr++) {\r
/* Initialize the Arrays for Transmit and Cancellation handling */\r
*(ControllerConfig[Controller].CancelPtr + MsgNr) = 0;\r
*(ControllerConfig[Controller].TxPtr + MsgNr) = 0;\r
\r
- /* Set the current FilterMaskPointer */\r
- CurFilterMaskPtr = CurControllerPtr->FilterMaskPtr;\r
/* Wait until Busy Flag is 0 */\r
while(CanBase[Controller]->IFx[IfRegId].COM & 0x00008000)\r
{\r
return;\r
}\r
}\r
- /* Configure the post-build defined MessageObjects */\r
- if(MsgNr < ControllerConfig[Controller].MessageBoxCount)\r
- { \r
- /* Check, if the next message object has the same values as the current, and if it is the last one */ \r
- if((MsgNr < (ControllerConfig[Controller].MessageBoxCount - 1)) &&\r
- (MsgBoxPtr->Direction == CAN_RECEIVE ) &&\r
- (MsgBoxPtr->Direction == (MsgBoxPtr + 1)->Direction ) &&\r
- (MsgBoxPtr->IdType == (MsgBoxPtr + 1)->IdType ) &&\r
- (MsgBoxPtr->IdValue == (MsgBoxPtr + 1)->IdValue ) &&\r
- (MsgBoxPtr->FilterMaskIndex == (MsgBoxPtr + 1)->FilterMaskIndex) &&\r
- (MsgBoxPtr->HandleType == (MsgBoxPtr + 1)->HandleType )\r
- )\r
- {\r
- /* EndOfBlock Bit will not be set */\r
- Eob = 0x00000000;\r
- }\r
- else\r
- {\r
- /* EndOfBlock Bit will be set */\r
- Eob = 0x00000080;\r
- }\r
- /* DLC=8, Use Mask only for receive, Set RxIE/TxIE depending on pre-config settings, Eob */\r
- CanBase[Controller]->IFx[IfRegId].MC = 0x00001008 | ControllerConfig[Controller].RxProc | (ControllerConfig[Controller].TxProc << 1) | Eob & ~(MsgBoxPtr->Direction >> 17);\r
- \r
- if(MsgBoxPtr->IdType == CAN_STANDARD) /* Standard Identifiers */\r
- {\r
- /* Only Standard-Ids are accepted, Set Mask */\r
- CanBase[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(CurFilterMaskPtr + MsgBoxPtr->FilterMaskIndex)) & 0x1FFFFFFF);\r
- /* Message valid, Id, Direction */\r
- CanBase[Controller]->IFx[IfRegId].ARB = 0x80000000 | ((MsgBoxPtr->IdValue & 0x7FF) << 18) | MsgBoxPtr->Direction;\r
- }\r
- else if(MsgBoxPtr->IdType == CAN_EXTENDED) /* Extended Identifiers */\r
- {\r
- /* Only Extended-Ids are accepted, Set Mask */\r
- CanBase[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(CurFilterMaskPtr + MsgBoxPtr->FilterMaskIndex)) & 0x1FFFFFFF);\r
- /* Message valid, Id, Direction */\r
- CanBase[Controller]->IFx[IfRegId].ARB = 0xC0000000 | (MsgBoxPtr->IdValue & 0x1FFFFFFF) | MsgBoxPtr->Direction; \r
- }\r
- else /* Mixed Identifiers */\r
- {\r
- /* Standard- and Mixed-Ids are accepted, Set Mask */\r
- CanBase[Controller]->IFx[IfRegId].MASK = 0x00000000 | ((*(CurFilterMaskPtr + MsgBoxPtr->FilterMaskIndex)) & 0x1FFFFFF);\r
- /* Message valid, Id, Direction */\r
- CanBase[Controller]->IFx[IfRegId].ARB = 0xC0000000 | (MsgBoxPtr->IdValue & 0x1FFFFFF) | MsgBoxPtr->Direction;\r
- }\r
- /* Start writing Mask, Arb, Control and Id bits */\r
- CanBase[Controller]->IFx[IfRegId].COM = 0x00F80000 | (MsgNr + 1);\r
- \r
- /* Save FilterMask reference of actual MessageObject */\r
- *(ControllerConfig[Controller].MaskRefPtr + MsgNr) = MsgBoxPtr->FilterMaskIndex;\r
-\r
- /* Increment Pointer to next MessageObject */\r
- MsgBoxPtr++;\r
- }\r
- else /* Configure all other MessageObjects to not valid */\r
- {\r
- /* Valid = 0 */\r
- CanBase[Controller]->IFx[IfRegId].ARB = 0x00000000;\r
- /* Start writing Arbitration Bits */\r
- CanBase[Controller]->IFx[IfRegId].COM = 0x00A80000 | (MsgNr + 1);\r
- }\r
- /* Use IFx[0] and IFx[1] alternating */\r
- IfRegId ^= 1;\r
+\r
+ // Initialize all message objects for this controller to invalid state.\r
+ /* Valid = 0 */\r
+ CanBase[Controller]->IFx[IfRegId].ARB = 0x00000000;\r
+ /* Start writing Arbitration Bits */\r
+ CanBase[Controller]->IFx[IfRegId].COM = 0x00A80000 | (MsgNr + 1);\r
+\r
+ /* Use IFx[0] and IFx[1] alternating */\r
+ IfRegId ^= 1;\r
+\r
}\r
+\r
+ /* Configure the HOHs for this controller. */\r
+ const Can_HardwareObjectType* hoh;\r
+ hoh = CanControllerConfigData[Controller].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ uint64 mbMask = hoh->Can_Arc_MbMask;\r
+ uint32 mbNr = 0;\r
+ uint32 nProcessedMb = 0;\r
+\r
+ // For every message object in this hoh\r
+ for(; mbMask != 0; mbMask >>= 1) {\r
+ mbNr++;\r
+ if (!(mbMask & 1)) {\r
+ // This message object is not part of this hoh.\r
+ continue;\r
+ }\r
+ nProcessedMb++;\r
+\r
+ // Check if this is the last message box for this hoh.\r
+ if((mbMask != 1) &&\r
+ (hoh->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)) {\r
+ /* EndOfBlock Bit will not be set */\r
+ Eob = 0x00000000;\r
+ }\r
+ else\r
+ {\r
+ /* EndOfBlock Bit will be set */\r
+ Eob = 0x00000080;\r
+ }\r
+\r
+ /* DLC=8, Use Mask only for receive, Set RxIE/TxIE depending on pre-config settings, Eob */\r
+ CanBase[Controller]->IFx[IfRegId].MC = 0x00001008 | CanControllerConfigData[Controller].CanRxProcessing | (CanControllerConfigData[Controller].CanTxProcessing << 1) | Eob & ~(hoh->CanObjectType >> 17);\r
+\r
+ if(hoh->CanIdType == CAN_ID_TYPE_STANDARD) /* Standard Identifiers */\r
+ {\r
+ /* Only Standard-Ids are accepted, Set Mask */\r
+ CanBase[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
+ /* Message valid, Id, Direction */\r
+ CanBase[Controller]->IFx[IfRegId].ARB = 0x80000000 | ((hoh->CanIdValue & 0x7FF) << 18) | hoh->CanObjectType;\r
+ }\r
+ else if(hoh->CanIdType == CAN_ID_TYPE_EXTENDED) /* Extended Identifiers */\r
+ {\r
+ /* Only Extended-Ids are accepted, Set Mask */\r
+ CanBase[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
+ /* Message valid, Id, Direction */\r
+ CanBase[Controller]->IFx[IfRegId].ARB = 0xC0000000 | (hoh->CanIdValue & 0x1FFFFFFF) | hoh->CanObjectType;\r
+ }\r
+ else /* Mixed Identifiers */\r
+ {\r
+ /* Standard- and Mixed-Ids are accepted, Set Mask */\r
+ CanBase[Controller]->IFx[IfRegId].MASK = 0x00000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFF);\r
+ /* Message valid, Id, Direction */\r
+ CanBase[Controller]->IFx[IfRegId].ARB = 0xC0000000 | (hoh->CanIdValue & 0x1FFFFFF) | hoh->CanObjectType;\r
+ }\r
+ /* Start writing Mask, Arb, Control and Id bits */\r
+ CanBase[Controller]->IFx[IfRegId].COM = 0x00F80000 | mbNr;\r
+\r
+ /* Use IFx[0] and IFx[1] alternating */\r
+ IfRegId ^= 1;\r
+\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+\r
+\r
/* Set Bit Timing Register */\r
- CanBase[Controller]->BTR = CurControllerPtr->CanTimeRegister;\r
+ CanBase[Controller]->BTR = Can_CalculateBTR(Controller);\r
+\r
/* Reset CCE Bit */\r
CanBase[Controller]->CTL &= ~0x00000040;\r
\r
- /* Switch Controller pointer to next ConfigSet */\r
- CurControllerPtr++;\r
-\r
#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
/* Switch Controller State to CANIF_CS_STOPPED */\r
ControllerMode[Controller] = CANIF_CS_STOPPED;\r
#endif\r
+\r
+ // Install interrupt handlers\r
+ TaskType tid;\r
+ if (CanControllerConfigData[Controller].CanControllerId == DCAN1) {\r
+ tid = Os_Arc_CreateIsr(Can1_InterruptHandler, 2 ,"DCAN1Level0");\r
+ Irq_AttachIsr2(tid, NULL, 16);\r
+\r
+ tid = Os_Arc_CreateIsr(Can1_InterruptHandler, 2, "DCAN1Level1");\r
+ Irq_AttachIsr2(tid, NULL, 29);\r
+\r
+ } else if (CanControllerConfigData[Controller].CanControllerId == DCAN2) {\r
+ tid = Os_Arc_CreateIsr(Can2_InterruptHandler, 2 ,"DCAN2Level0");\r
+ Irq_AttachIsr2(tid, NULL, 35);\r
+\r
+ tid = Os_Arc_CreateIsr(Can2_InterruptHandler, 2, "DCAN2Level1");\r
+ Irq_AttachIsr2(tid, NULL, 42);\r
+\r
+ } else if (CanControllerConfigData[Controller].CanControllerId == DCAN3) {\r
+ tid = Os_Arc_CreateIsr(Can3_InterruptHandler, 2 ,"DCAN3Level0");\r
+ Irq_AttachIsr2(tid, NULL, 45);\r
+\r
+ tid = Os_Arc_CreateIsr(Can3_InterruptHandler, 2, "DCAN3Level1");\r
+ Irq_AttachIsr2(tid, NULL, 55);\r
+\r
+ }\r
+\r
}\r
#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
/* Switch Module State to CAN_READY */\r
#endif\r
\r
\r
- // ARC INSTALL HANDLERS\r
- TaskType tid;\r
- tid = Os_Arc_CreateIsr(CAN1_INTERRUPTHANDLER_0, 2 ,"Can0Level0");\r
- Irq_AttachIsr2(tid, NULL, 16);\r
-\r
- tid = Os_Arc_CreateIsr(CAN1_INTERRUPTHANDLER_0, 2, "Can0Level1");\r
- Irq_AttachIsr2(tid, NULL, 29);\r
\r
}\r
\r
\r
\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can_InitController */\r
-/* Service Id: 0x02 */\r
-/* Execution: Synchronous */\r
-/* Re-entrant: No */\r
-/* Description: Initializes only CAN cantroller specific settings */\r
-/* Controller: CAN controller to be initialized */\r
-/* Config: Pointer to controller configuration */\r
-/* Return Value: None */\r
-/* Remarks: -/- */\r
-/* */\r
-\r
-void CAN_INITCONTROLLER(uint8 Controller, const Can_ControllerConfigType* Config)\r
+void Can_InitController(uint8 Controller, const Can_ControllerConfigType* Config)\r
{\r
- uint32 *CurMaskRef;\r
uint8 MsgNr;\r
uint32 ErrCounter;\r
\r
Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 2, CAN_E_UNINIT);\r
return;\r
}\r
- if(Controller >= CAN_CONTROLLER_COUNT)\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
{\r
Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 2, CAN_E_PARAM_CONTROLLER);\r
return;\r
}\r
#endif \r
\r
- CurMaskRef = ControllerConfig[Controller].MaskRefPtr;\r
ErrCounter = CAN_TIMEOUT_DURATION;\r
\r
- for(MsgNr = 0; MsgNr < ControllerConfig[Controller].MessageBoxCount; MsgNr++)\r
- {\r
+ //for(MsgNr = 0; MsgNr < ControllerConfig[Controller].MessageBoxCount; MsgNr++)\r
+ const Can_HardwareObjectType* hoh;\r
+ hoh = CanControllerConfigData[Controller].Can_Arc_Hoh;\r
+ uint64 mbMask = hoh->Can_Arc_MbMask;\r
+ uint32 nProcessedMb = 0;\r
+ MsgNr = 0;\r
+\r
+ // For every message object in this hoh\r
+ for(; mbMask != 0; mbMask >>= 1) {\r
+ if (!(mbMask & 1)) {\r
+ // This message object is not part of this hoh.\r
+ continue;\r
+ }\r
+ MsgNr++;\r
+ nProcessedMb++;\r
+\r
/* Wait until Busy Flag is 0 */\r
while(CanBase[Controller]->IFx[IfRegId].COM & 0x00008000)\r
{\r
}\r
}\r
/* Read actual MaskRegister value of MessageObject */\r
- CanBase[Controller]->IFx[IfRegId].COM = 0x004C0000 | (MsgNr + 1);\r
+ CanBase[Controller]->IFx[IfRegId].COM = 0x004C0000 | (MsgNr);\r
\r
/* Wait until Busy Flag is 0 */\r
while(CanBase[Controller]->IFx[IfRegId].COM & 0x00008000)\r
}\r
CanBase[Controller]->IFx[IfRegId].MASK &= 0xD0000000;\r
/* Set new Mask */\r
- CanBase[Controller]->IFx[IfRegId].MASK |= *(Config->FilterMaskPtr + *CurMaskRef) & 0x1FFFFFFF;\r
+ CanBase[Controller]->IFx[IfRegId].MASK |= (*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF;\r
/* Write new Mask to MaskRegister */\r
- CanBase[Controller]->IFx[IfRegId].COM = 0x00C80000 | (MsgNr + 1); \r
- \r
- CurMaskRef++;\r
+ CanBase[Controller]->IFx[IfRegId].COM = 0x00C80000 | (MsgNr);\r
\r
IfRegId ^= 1;\r
}\r
+\r
/* Wait until Busy Flag is 0 */\r
while(CanBase[Controller]->IFx[IfRegId].COM & 0x00008000)\r
{\r
/* Set CCE Bit to allow access to BitTiming Register (Init already set, in mode "stopped") */\r
CanBase[Controller]->CTL |= 0x00000040;\r
/* Set Bit Timing Register */\r
- CanBase[Controller]->BTR = Config->CanTimeRegister;\r
+ CanBase[Controller]->BTR = Can_CalculateBTR(Controller);\r
/* Clear CCE Bit */\r
CanBase[Controller]->CTL &= ~0x00000040;\r
\r
}\r
\r
\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can_SetControllerMode */\r
-/* Service Id: 0x03 */\r
-/* Execution: Asynchronous */\r
-/* Re-entrant: No */\r
-/* Descrpition: Performs software triggered state transitions */\r
-/* Controller: CAN controller for which the status shall be changed */\r
-/* Transition: Transition to be done */\r
-/* Return Value: - CAN_OK: transition initiated */\r
-/* - CAN_NOT_OK: error or wakeup during transition to 'sleep' */\r
-/* Remarks: -/- */\r
-/* */\r
-\r
Can_ReturnType Can_SetControllerMode(uint8 Controller, Can_StateTransitionType Transition)\r
{\r
Can_ReturnType Status = CAN_OK;\r
Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 3, CAN_E_UNINIT);\r
return CAN_NOT_OK;\r
}\r
- if(Controller >= CAN_CONTROLLER_COUNT)\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
{\r
Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 3, CAN_E_PARAM_CONTROLLER);\r
return CAN_NOT_OK;\r
}\r
\r
\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can_DisableControllerInterrupts */\r
-/* Service Id: 0x04 */\r
-/* Execution: Synchronous */\r
-/* Re-entrant: Yes */\r
-/* Description: Disables all interrupts for this controller */\r
-/* Controller: CAN controller for which interrupts shall be disabled */\r
-/* Return Value: None */\r
-/* Remarks: -/- */\r
-/* */\r
-\r
void Can_DisableControllerInterrupts(uint8 Controller)\r
{\r
#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 4, CAN_E_UNINIT);\r
return;\r
}\r
- if(Controller >= CAN_CONTROLLER_COUNT)\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
{\r
Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 4, CAN_E_PARAM_CONTROLLER);\r
return;\r
IntDisableCount[Controller]++;\r
}\r
\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can_EnableControllerInterrupts */\r
-/* Service Id: 0x05 */\r
-/* Execution: Synchronous */\r
-/* Re-entrant: Yes */\r
-/* Description: Enables all allowed interrupts for this controller */\r
-/* Controller: CAN controller for which interrupts shall be re-enabled */\r
-/* Return Value: None */\r
-/* Remarks: -/- */\r
-/* */\r
-\r
void Can_EnableControllerInterrupts(uint8 Controller)\r
{\r
#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 5, CAN_E_UNINIT);\r
return;\r
}\r
- if(Controller >= CAN_CONTROLLER_COUNT)\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
{\r
Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 5, CAN_E_PARAM_CONTROLLER);\r
return;\r
}\r
\r
\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can_Cbk_CheckWakeup */\r
-/* Service Id: 0x0b */\r
-/* Execution: Synchronous */\r
-/* Re-entrant: No */\r
-/* Description: Checks if a wakeup has occurred for the given controller */\r
-/* Controller: CAN controller to be checked for wakeup */\r
-/* Return Value: - E_OK: Wakeup was detected for given controller */\r
-/* - E_NOT_OK: No Wakeup was detected */\r
-/* Remarks: -/- */\r
-/* */\r
-\r
void Can_Cbk_CheckWakeup(uint8 Controller)\r
{\r
- /*\r
+ /* TODO not supported yet.\r
#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
- if(Controller >= CAN_CONTROLLER_COUNT)\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
{\r
Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 0x0B, CAN_E_PARAM_CONTROLLER);\r
return CAN_NOT_OK;\r
}\r
\r
\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can_Write */\r
-/* Service Id: 0x06 */\r
-/* Execution: Synchronous */\r
-/* Re-entrant: Yes (thread-safe) */\r
-/* Description: -- */\r
-/* Hth: HW-transmit handle to be used for transmit */\r
-/* PduInfo: Pointer to SDU user memory, DLC and Identifier */\r
-/* Return Value: - CAN_OK: Write command has been accepted */\r
-/* - CAN_NOT_OK: Development error occured */\r
-/* - CAN_BUSY: No TX hw buffer available or preemptive call */ \r
-/* Remarks: -/- */\r
-/* */\r
-\r
Can_ReturnType Can_Write(Can_Arc_HTHType Hth, Can_PduType *PduInfo)\r
{\r
uint32 ErrCounter;\r
uint8 ControllerId;\r
uint8 MsgNr;\r
- uint32 CancelId;\r
- uint8 CancelNr; \r
uint32 ArbRegValue;\r
uint8 DataByteIndex;\r
uint8 *CurSduPtr;\r
Can_PduType *CurPduArrayPtr;\r
uint8 *CurCancelRqstPtr;\r
uint8 *CurTxRqstPtr;\r
- Can_MessageObjectType *CurMsgBoxPtr;\r
\r
CurSduPtr = PduInfo->sdu;\r
- CurMsgBoxPtr = CurConfig->MessageBoxPtr + Hth;\r
ErrCounter = CAN_TIMEOUT_DURATION;\r
\r
/* DET Error Check */\r
Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 6, CAN_E_PARAM_DLC);\r
return CAN_NOT_OK; \r
}\r
- if(CurMsgBoxPtr->Direction != CAN_TRANSMIT)\r
- {\r
- Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 6, CAN_E_PARAM_HANDLE);\r
- return CAN_NOT_OK;\r
- } \r
#endif\r
\r
- ControllerId = CurMsgBoxPtr->Controller;\r
+ ControllerId = Can_FindControllerId(Hth);\r
\r
- MsgNr = Hth - ControllerConfig[ControllerId].FirstHandle;\r
+ const Can_HardwareObjectType *hoh = Can_FindTxHoh(Hth);\r
\r
- CurPduArrayPtr = ControllerConfig[ControllerId].PduPtr + MsgNr;\r
- CurCancelRqstPtr = ControllerConfig[ControllerId].CancelPtr + MsgNr;\r
- CurTxRqstPtr = ControllerConfig[ControllerId].TxPtr + MsgNr;\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(hoh->CanObjectType != CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 6, CAN_E_PARAM_HANDLE);\r
+ return CAN_NOT_OK;\r
+ }\r
+#endif\r
+ uint64 mbMask = hoh->Can_Arc_MbMask;\r
+ MsgNr = 0;\r
+ for(; mbMask != 0; mbMask >>= 1) {\r
+ if (!(mbMask & 1)) {\r
+ continue; // This message object is not part of this hoh.\r
+ }\r
+ // Just use the first message object.\r
+ MsgNr++;\r
+ }\r
+\r
+ CurPduArrayPtr = ControllerConfig[ControllerId].PduPtr + (MsgNr - 1);\r
+ CurCancelRqstPtr = ControllerConfig[ControllerId].CancelPtr + (MsgNr - 1);\r
+ CurTxRqstPtr = ControllerConfig[ControllerId].TxPtr + (MsgNr - 1);\r
\r
/* Bring Id Value to appropriate format and set ArbRegValue */\r
if(PduInfo->id & 0x80000000)\r
/* Check if TxRqst Bit of MsgObject is set */\r
if(CanBase[ControllerId]->TRx[MsgNr >> 5] & (1 << (MsgNr & 0x1F)))\r
{\r
-\r
-#if(CAN_MULTIPLEXED_TRANSMISSION == STD_ON)\r
-\r
- CancelId = ArbRegValue & 0x1FFFFFFF;\r
- CancelNr = MsgNr;\r
-\r
- for(MsgNr = ControllerConfig[ControllerId].MessageBoxCount; MsgNr < ControllerConfig[ControllerId].MaxBoxes; MsgNr++)\r
- {\r
- /* Read actual MessageObject status: Data, Arbitration, Control */\r
- CanBase[ControllerId]->IFx[IfRegId].COM = 0x00330000 | (MsgNr + 1); \r
- /* Wait until Busy Flag is 0 */\r
- while(CanBase[ControllerId]->IFx[IfRegId].COM & 0x00008000)\r
- {\r
- ErrCounter--;\r
- if(ErrCounter == 0)\r
- {\r
- Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED);\r
- ErrCounter = CAN_TIMEOUT_DURATION;\r
- return CAN_NOT_OK;\r
- }\r
- }\r
-\r
- /* If MessageObject is free, use it */\r
- if(!(CanBase[ControllerId]->IFx[IfRegId].MC & 0x00000100))\r
- {\r
- CurPduArrayPtr = ControllerConfig[ControllerId].PduPtr + MsgNr;\r
- break;\r
- }\r
- /* Check if Id of MessageObject is higher */\r
- if((CanBase[ControllerId]->IFx[IfRegId].ARB & 0x1FFFFFFF) > CancelId )\r
- {\r
- /* Save the highest ID (low priority) */\r
- CancelId = CanBase[ControllerId]->IFx[IfRegId].ARB & 0x1FFFFFFF;\r
- /* and corresponding message number */\r
- CancelNr = MsgNr;\r
- }\r
- }\r
- if(MsgNr == ControllerConfig[ControllerId].MaxBoxes)\r
- {\r
-#if(CAN_HW_TRANSMIT_CANCELLATION == STD_ON)\r
- /* Clear TxRqst */\r
- CanBase[ControllerId]->IFx[IfRegId].MC &= ~0x00000100;\r
- /* Transfer Control bits to MessageObject */\r
- CanBase[ControllerId]->IFx[IfRegId].COM = 0x90000000 | (CancelNr + 1);\r
- \r
- if(ControllerConfig[ControllerId].TxProc == INTERRUPT)\r
- {\r
- /* Set CurPduPtr to Pdu of object to cancel */ \r
- CurPduArrayPtr = ControllerConfig[ControllerId].PduPtr + CancelNr;\r
- /* Wait until Busy Flag is 0 */\r
- while(CanBase[ControllerId]->IFx[IfRegId].COM & 0x00008000)\r
- {\r
- ErrCounter--;\r
- if(ErrCounter == 0)\r
- {\r
- Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED);\r
- ErrCounter = CAN_TIMEOUT_DURATION;\r
- return CAN_NOT_OK;\r
- }\r
- }\r
- /* Notification about cancellation of object */\r
- CanIf_CancelTxConfirmation((const Can_PduType *)CurPduArrayPtr);\r
- }\r
- else\r
- {\r
- /* Set CancelPointer to Position of cancelled Object */\r
- CurCancelRqstPtr = ControllerConfig[ControllerId].CancelPtr + CancelNr;\r
- /* Set Arrayelement to 1 to indicate cancellation request */\r
- *CurCancelRqstPtr = 1;\r
- }\r
-#endif\r
- }\r
-#elif(CAN_HW_TRANSMIT_CANCELLATION == STD_ON)\r
- \r
- /* Wait until Busy Flag is 0 */\r
- while(CanBase[ControllerId]->IFx[IfRegId].COM & 0x00008000)\r
- {\r
- ErrCounter--;\r
- if(ErrCounter == 0)\r
- {\r
- Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED);\r
- ErrCounter = CAN_TIMEOUT_DURATION;\r
- return CAN_NOT_OK;\r
- }\r
- }\r
-\r
- /* Read actual MessageObject status: Data, Arbitration, Control */\r
- CanBase[ControllerId]->IFx[IfRegId].COM = 0x00330000 | (MsgNr + 1);\r
-\r
- /* Wait until Busy Flag is 0 */\r
- while(CanBase[ControllerId]->IFx[IfRegId].COM & 0x00008000)\r
- {\r
- ErrCounter--;\r
- if(ErrCounter == 0)\r
- {\r
- Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED);\r
- ErrCounter = CAN_TIMEOUT_DURATION;\r
- return CAN_NOT_OK;\r
- }\r
- } \r
- \r
- /* Check if actual message has higher priority */\r
- if((ArbRegValue & 0x1FFFFFFF) < (CanBase[ControllerId]->IFx.ARB & 0x1FFFFFFF))\r
- {\r
- /* Clear TxRqst */\r
- CanBase[ControllerId]->IFx[IfRegId].MC &= ~0x00000100;\r
- /* Transfer Control bits to MessageObject */\r
- CanBase[ControllerId]->IFx[IfRegId].COM = 0x90000000 | (MsgNr + 1);\r
- \r
- if(ControllerConfig[ControllerId].TxProc == INTERRUPT)\r
- {\r
- /* Wait until Busy Flag is 0 */\r
- while(CanBase[ControllerId]->IFx[IfRegId].COM & 0x00008000)\r
- {\r
- ErrCounter--;\r
- if(ErrCounter == 0)\r
- {\r
- Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED);\r
- ErrCounter = CAN_TIMEOUT_DURATION;\r
- return CAN_NOT_OK;\r
- }\r
- } \r
- /* Notification about cancellation of object */\r
- CanIf_CancelTxConfirmation((const Can_PduType *)CurPduArrayPtr);\r
- }\r
- else\r
- {\r
- /* Set Arrayelement to 1 to indicate cancellation request */\r
- *CurCancelRqstPtr = 1;\r
- }\r
- }\r
-#endif\r
return CAN_BUSY;\r
}\r
\r
}\r
\r
/* Set NewDat, TxIE (dep on ControllerConfig), TxRqst, EoB and DLC */\r
- CanBase[ControllerId]->IFx[IfRegId].MC = 0x00000180 | (0x000F & PduInfo->length) | (ControllerConfig[ControllerId].TxProc << 1);\r
+ CanBase[ControllerId]->IFx[IfRegId].MC = 0x00000180 | (0x000F & PduInfo->length) | (CanControllerConfigData[ControllerId].CanTxProcessing << 1);\r
\r
/* Set ArbitrationRegister */\r
CanBase[ControllerId]->IFx[IfRegId].ARB = ArbRegValue;\r
}\r
\r
/* Start transmission to MessageRAM */\r
- CanBase[ControllerId]->IFx[IfRegId].COM = 0x00BF0000 | (MsgNr + 1);\r
+ CanBase[ControllerId]->IFx[IfRegId].COM = 0x00BF0000 | MsgNr;\r
\r
/* Save the PduInfo in PduArray, so that messages can be identified later */\r
*CurPduArrayPtr = *PduInfo;\r
}\r
\r
\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can_MainFunction_Write */\r
-/* Service Id: 0x01 */\r
-/* Timing: FIXED_CYCLIC */\r
-/* Description: Polling of TX confirmation and TX cancellation confirmation */\r
-/* Return Value: None */\r
-/* Remarks: -/- */\r
-/* */\r
-\r
-void CAN_MAINFUNCTION_WRITE()\r
+void Can_MainFunction_Write()\r
{\r
-#if 0\r
- uint8 Controller;\r
- uint8 MsgNr;\r
- Can_PduType *CurPduPtr;\r
-\r
-#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
- if(ModuleState == CAN_UNINIT)\r
- {\r
- Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 1, CAN_E_UNINIT);\r
- return;\r
- }\r
-#endif \r
- /* Check all controllers */\r
- for(Controller = 0; Controller < CAN_CONTROLLER_COUNT; Controller++)\r
- {\r
- /* Check all MessageObjects */\r
- for(MsgNr = 0; MsgNr < ControllerConfig[Controller].MaxBoxes; MsgNr++)\r
- {\r
- /* Check if a transmission was initiated for this MessageObject */\r
- if(*(ControllerConfig[Controller].TxPtr + MsgNr) == 1)\r
- {\r
- /* Check if TxRqst Bit has already been reset */\r
- if(!(CanBase[Controller]->TRx[MsgNr >> 5] & (1 << (MsgNr & 0x1F))))\r
- {\r
- /* Reset swTxRqst */\r
- *(ControllerConfig[Controller].TxPtr + MsgNr) = 0;\r
- \r
- CurPduPtr = ControllerConfig[Controller].PduPtr + MsgNr;\r
- /* A Message was successfully transmitted */\r
- CanIf_TxConfirmation(CurPduPtr->swPduHandle);\r
- }\r
- }\r
- /* Check if a cancellation was initiated for this MessageObject */\r
- if(*(ControllerConfig[Controller].CancelPtr + MsgNr) == 1)\r
- {\r
- /* Check if TxRqst Bit has already been reset */\r
- if(!(CanBase[Controller]->TRx[MsgNr >> 5] & (1 << (MsgNr & 0x1F))))\r
- {\r
- /* Reset swCancelRqst */\r
- *(ControllerConfig[Controller].CancelPtr + MsgNr) = 0;\r
- \r
- CurPduPtr = ControllerConfig[Controller].PduPtr + MsgNr;\r
- /* A Message was successfully transmitted */\r
- CanIf_CancelTxConfirmation(CurPduPtr); \r
- }\r
- }\r
- }\r
- }\r
-#endif\r
+ // Not supported\r
}\r
\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can_MainFunction_Read */\r
-/* Service Id: 0x08 */\r
-/* Timing: FIXED_CYCLIC */\r
-/* Description: Polling of RX indications */\r
-/* Return Value: None */\r
-/* Remarks: -/- */\r
-/* */\r
-\r
-void CAN_MAINFUNCTION_READ()\r
+void Can_MainFunction_Read()\r
{\r
-#if 0\r
- uint8 Controller;\r
- uint8 MsgNr;\r
- Can_MessageObjectType *CurMsgBoxPtr;\r
- uint8 MsgDlc;\r
- uint32 Identifier;\r
- uint8 DataByteIndex;\r
- uint8 *SduPtr;\r
- uint32 ErrCounter; \r
- \r
-\r
-#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
- if(ModuleState == CAN_UNINIT)\r
- {\r
- Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 8, CAN_E_UNINIT);\r
- return;\r
- }\r
-#endif\r
-\r
- CurMsgBoxPtr = CurConfig->MessageBoxPtr;\r
- \r
- for(Controller = 0; Controller < CAN_CONTROLLER_COUNT; Controller++)\r
- {\r
- for(MsgNr = 0; MsgNr < ControllerConfig[Controller].MessageBoxCount; MsgNr++)\r
- {\r
- /* Check if NewDat Bit is set and if MessageObject is Receive Object */\r
- if((CanBase[Controller]->NDx[MsgNr >> 5] & (1 << (MsgNr & 0x1F))) && (CurMsgBoxPtr->Direction == RECEIVE))\r
- {\r
- \r
- /* Read Arbitration, Control and Data Bits and clear IntPnd and NewDat*/\r
- CanBase[Controller]->IFx[IfRegId].COM = 0x003F0000 | (MsgNr + 1);\r
- \r
- ErrCounter = CAN_TIMEOUT_DURATION;\r
- /* Wait until Busy Flag is 0 */\r
- while(CanBase[Controller]->IFx[IfRegId].COM & 0x8000)\r
- {\r
- ErrCounter--;\r
- if(ErrCounter == 0)\r
- {\r
- Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED);\r
- return;\r
- }\r
- }\r
- /* Extended Id */\r
- if(CanBase[0]->IFx[IfRegId].ARB & 0x40000000)\r
- {\r
- /* Bring Id to standardized format (MSB marks extended Id) */\r
- Identifier = (CanBase[0]->IFx[IfRegId].ARB & 0x1FFFFFFF) | 0x80000000;\r
- }\r
- /* Standard Id */\r
- else\r
- {\r
- /* Bring Id to standardized format (MSB marks extended Id) */\r
- Identifier = (CanBase[0]->IFx[IfRegId].ARB & 0x1FFC0000) >> 18;\r
- }\r
- /* DLC (Max 8) */\r
- MsgDlc = CanBase[0]->IFx[IfRegId].MC & 0x000F;\r
- if(MsgDlc > 8)\r
- {\r
- MsgDlc = 8;\r
- }\r
- /* Let SduPtr point to Shadow Buffer */\r
- SduPtr = RxShadowBuf;\r
-\r
- /* Copy Message Data to Shadow Buffer */\r
- for(DataByteIndex = 0; DataByteIndex < MsgDlc; DataByteIndex++)\r
- {\r
- RxShadowBuf[DataByteIndex] = CanBase[0]->IFx[IfRegId].DATx[ElementIndex[DataByteIndex]];\r
- }\r
- /* Indicate successful Reception */\r
- CanIf_RxIndication(MsgNr, Identifier, MsgDlc, SduPtr);\r
- } \r
- CurMsgBoxPtr++;\r
- }\r
- }\r
-#endif\r
+ // Not supported\r
}\r
\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can_MainFunction_BusOff */\r
-/* Service Id: 0x09 */\r
-/* Timing: FIXED_CYCLIC */\r
-/* Description: Polling of bus-off events */\r
-/* Return Value: None */\r
-/* Remarks: -/- */\r
-/* */\r
-\r
-void CAN_MAINFUNCTION_BUSOFF()\r
+void Can_MainFunction_BusOff()\r
{\r
- uint8 Controller;\r
-\r
-/* DET Error Check */\r
-#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
- if(ModuleState == CAN_UNINIT)\r
- {\r
- Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 9, CAN_E_UNINIT);\r
- return;\r
- } \r
-#endif\r
- \r
- for(Controller = 0 ; Controller < CAN_CONTROLLER_COUNT; Controller++)\r
- {\r
- /* Bus Off */\r
- if(CanBase[Controller]->SR & 0x00000080)\r
- {\r
-#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
- ControllerMode[Controller] = CANIF_CS_STOPPED;\r
-#endif\r
- CanIf_ControllerBusOff(Controller);\r
- }\r
- }\r
+ // Not supported\r
}\r
\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can_MainFunction_Wakeup */\r
-/* Service Id: 0x0a */\r
-/* Timing: FIXED_CYCLIC */\r
-/* Description: Polling of wake-up events */\r
-/* Return Value: None */\r
-/* Remarks: -/- */\r
-/* */\r
-\r
-void CAN_MAINFUNCTION_WAKEUP()\r
+void Can_MainFunction_Wakeup()\r
{\r
- uint8 Controller;\r
-\r
-/* DET Error Check */\r
-#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
- if(ModuleState == CAN_UNINIT)\r
- {\r
- Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 0xA, CAN_E_UNINIT);\r
- return;\r
- } \r
-#endif\r
-\r
- for(Controller = 0 ; Controller < CAN_CONTROLLER_COUNT; Controller++)\r
- {\r
- /* Check WakeUp Pending */\r
- if(CanBase[Controller]->SR & 0x200)\r
- {\r
- /* Set Init Bit, so that Controller is in Stop state */\r
- CanBase[Controller]->CTL |= 0x1;\r
-#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
- ControllerMode[Controller] = CANIF_CS_STOPPED;\r
-#endif\r
- //EcuM_CheckWakeUp(ControllerConfig[Controller].WakeupSrc);\r
- }\r
- }\r
+ // Not supported\r
}\r
\r
\r
-\r
-\r
-/*----------------------------------------------------------------------------*/\r
-/* Function Name: Can2_InterruptHandler_0 */\r
-/* Description: CAN Node 2 Level 0 Interrupt Service Routine */\r
-/* Return Value: None */\r
-/* Remarks: -/- */\r
-/* */\r
-#ifdef CanController_1\r
-//#pragma INTERRUPT(CAN2_INTERRUPTHANDLER_0,IRQ)\r
-\r
-void CAN2_INTERRUPTHANDLER_0()\r
-{\r
-\r
- uint32 ErrCounter;\r
- uint32 MsgNr;\r
- uint32 MsgId;\r
- uint8 MsgDlc;\r
- uint8 DataByteIndex;\r
- uint8 *SduPtr; \r
-\r
- ErrCounter = CAN_TIMEOUT_DURATION;\r
- \r
- if(CanBase[1]->IR == 0x8000)\r
- {\r
- /* WakeUp Pending */\r
- if(CanBase[1]->SR & 0x200)\r
- {\r
-#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
- ControllerMode[1] = CANIF_CS_STOPPED;\r
-#endif\r
- /* Set Init Bit, so that Controller is in Stop state */\r
- CanBase[1]->CTL |= 0x1;\r
- // EcuM_CheckWakeUp(ControllerConfig[1].WakeupSrc);\r
- }\r
- /* Bus Off */\r
- if(CanBase[1]->SR & 0x080)\r
- {\r
-#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
- ControllerMode[1] = CANIF_CS_STOPPED;\r
-#endif\r
- CanIf_ControllerBusOff(1);\r
- }\r
- }\r
- else\r
- {\r
- MsgNr = CanBase[1]->IR;\r
- \r
- /* Read Arbitration, Control and Data Bits and clear IntPnd */\r
- CanBase[1]->IFx[IfRegId].COM = 0x003F0000 | MsgNr;\r
- \r
- /* Wait until Busy Flag is 0 */\r
- while(CanBase[1]->IFx[IfRegId].COM & 0x8000)\r
- {\r
- ErrCounter--;\r
- if(ErrCounter == 0)\r
- {\r
- Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED);\r
- ErrCounter = CAN_TIMEOUT_DURATION;\r
- return;\r
- }\r
- }\r
- \r
- /* Transmit Object */\r
- if(CanBase[1]->IFx[IfRegId].ARB & 0x20000000)\r
- {\r
- /* Reset TxRqst-Array Element */\r
- TxRqstArray_1[MsgNr - 1] = 0;\r
- /* A Message was successfully transmitted */\r
- CanIf_TxConfirmation(PduInfoArray_1[MsgNr - 1].swPduHandle);\r
- } \r
- /* Receive Object */\r
- else\r
- {\r
- /* Extended Id */\r
- if(CanBase[1]->IFx[IfRegId].ARB & 0x40000000)\r
- {\r
- /* Bring Id to standardized format (MSB marks extended Id) */\r
- MsgId = (CanBase[1]->IFx[IfRegId].ARB & 0x1FFFFFFF) | 0x80000000;\r
- }\r
- /* Standard Id */\r
- else\r
- {\r
- /* Bring Id to standardized format (MSB marks extended Id) */\r
- MsgId = (CanBase[1]->IFx[IfRegId].ARB & 0x1FFC0000) >> 18;\r
- }\r
- /* DLC (Max 8) */\r
- MsgDlc = CanBase[1]->IFx[IfRegId].MC & 0x000F;\r
- if(MsgDlc > 8)\r
- {\r
- MsgDlc = 8;\r
- }\r
- /* Let SduPtr point to Shadow Buffer */\r
- SduPtr = RxShadowBuf;\r
-\r
- /* Copy Message Data to Shadow Buffer */\r
- for(DataByteIndex = 0; DataByteIndex < MsgDlc; DataByteIndex++)\r
- {\r
- RxShadowBuf[DataByteIndex] = CanBase[1]->IFx[IfRegId].DATx[ElementIndex[DataByteIndex]];\r
- }\r
- /* Indicate successful Reception */\r
- CanIf_RxIndication(MsgNr - 1, MsgId, MsgDlc, SduPtr);\r
- }\r
- }\r
-\r
-}\r
-#endif\r
#ifndef IRQ_TYPES_H\r
#define IRQ_TYPES_H\r
\r
+#define SYS_SWI_NR 21\r
+\r
#define IrqGetCurrentInterruptSource() \\r
- (((uint8)vimREG->IRQIVEC) - 1)\r
+ (((volatile sint8)vimREG->IRQIVEC) - 1)\r
\r
/** IrqActivateChannel turns the selected channel on in the VIM */\r
#define IrqActivateChannel(_channel) \\r
- vimREG->REQMASKSET0 |= (1 << _channel)\r
+ if (_channel > 31) { \\r
+ vimREG->REQMASKSET1 |= (1 << (_channel - 32)); \\r
+ } else { \\r
+ vimREG->REQMASKSET0 |= (1 << _channel); \\r
+ }\r
\r
\r
/** IrqDeactivateChannel turns the selected channel off in the VIM */\r
#define IrqDeactivateChannel(_channel) \\r
- vimREG->REQMASKCLR0 = (1 << _channel)\r
+ if (_channel > 31) { \\r
+ vimREG->REQMASKCLR1 = (1 << (_channel - 32)); \\r
+ } else { \\r
+ vimREG->REQMASKCLR0 = (1 << _channel); \\r
+ }\r
\r
\r
#define Irq_SOI() \\r
- uint8 channel = IrqGetCurrentInterruptSource(); \\r
+ sint8 channel = IrqGetCurrentInterruptSource(); \\r
IrqDeactivateChannel(channel)\r
\r
\r
\r
\r
\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** STM32 specific Interrupt Numbers *********************************************************/\r
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
- TAMPER_IRQn = 2, /*!< Tamper Interrupt */\r
- RTC_IRQn = 3, /*!< RTC global Interrupt */\r
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
- RCC_IRQn = 5, /*!< RCC global Interrupt */\r
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
- DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */\r
- DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */\r
- DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */\r
- DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */\r
- DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
- DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
- DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
-\r
-#ifdef STM32F10X_LD\r
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
-#endif /* STM32F10X_LD */\r
-\r
-#ifdef STM32F10X_MD\r
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
-#endif /* STM32F10X_MD */\r
-\r
-#ifdef STM32F10X_HD\r
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
- TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */\r
- TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */\r
- TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */\r
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
- ADC3_IRQn = 47, /*!< ADC3 global Interrupt */\r
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
- UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
- UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
- TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
- TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
- DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
-#endif /* STM32F10X_HD */\r
-\r
-#ifdef STM32F10X_CL\r
- CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
- CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */\r
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
- UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
- UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
- TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
- TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
- DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */\r
- DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */\r
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r
- OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */\r
-#endif /* STM32F10X_CL */\r
-} IRQn_Type;\r
-\r
-typedef IRQn_Type IrqType;\r
-\r
-/* Offset from start of exceptions to interrupts\r
- * Exceptions have negative offsets while interrupts have positive\r
- */\r
-//#define IRQ_INTERRUPT_OFFSET 16\r
-\r
/* Total number of interrupts and exceptions\r
*/\r
#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS 65\r
PERIPHERAL_CLOCK_AHB,\r
PERIPHERAL_CLOCK_APB1,\r
PERIPHERAL_CLOCK_APB2,\r
+ PERIPHERAL_CLOCK_CAN,\r
+ PERIPHERAL_CLOCK_DCAN1,\r
+ PERIPHERAL_CLOCK_DCAN2,\r
+ PERIPHERAL_CLOCK_DCAN3\r
} McuE_PeriperalClock_t;\r
\r
-\r
typedef enum {\r
CPU_0=0,\r
} Cpu_t;\r
projects / arc.git / commitdiff