1 /* -------------------------------- Arctic Core ------------------------------
\r
2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
\r
4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
\r
6 * This source code is free software; you can redistribute it and/or modify it
\r
7 * under the terms of the GNU General Public License version 2 as published by the
\r
8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
\r
10 * This program is distributed in the hope that it will be useful, but
\r
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
\r
14 * -------------------------------- Arctic Core ------------------------------*/
\r
22 .global Default_Handler
\r
24 /* Addresses used to setup RAM */
\r
31 /* The address of the stack to use in all modes. */
\r
36 * @brief This is the code that gets called when the processor first
\r
37 * starts execution following a reset event. Only the absolutely
\r
38 * necessary set is performed, after which the application
\r
39 * supplied main() routine is called.
\r
43 .section .text.Reset_Handler
\r
45 .type Reset_Handler, %function
\r
49 /* Set big endian state */
\r
52 /* Initialize core registers.
\r
53 This is done to avoid mismatch between lockstep CPU and ordinary CPU
\r
77 orr r12, r1, #0x0002
\r
80 orr r12, r1, #0x0007
\r
83 orr r12, r1, #0x000B
\r
86 orr r12, r1, #0x0003
\r
90 /* System level configuration
\r
91 This mainly involves setting instruction mode for exceptions and interrupts.
\r
93 mrc p15,0,r11,c1,c0,0 /* Read current system configuration */
\r
94 mov r12, #0x40000000 /* Set THUMB instruction set mode for interrupts and exceptions */
\r
96 mcr p15,0,r12,c1,c0,0 /* Write new configuration */
\r
99 /* Initialize stack pointers.
\r
100 This is done for all processor modes. Note that we only use one stack pointer.
\r
101 In reality this means that no mode except USER and SYS is allowed to do anythin on the stack.
\r
102 IRQ mode handles its own stack in the interrupt routine.
\r
130 First the initialized RAM is copied from flash to RAM.
\r
131 Then the zeroed RAM is erased.
\r
133 ldr r0, =_sdata /* r0 holds start of data in ram */
\r
134 ldr r3, =_edata /* r3 holds end of data in ram */
\r
135 ldr r5, =_sidata /* r5 start of data in flash */
\r
136 movs r1, #0 /* r1 is the counter */
\r
140 ldr r4, [r5, r1] /* read current position in flash */
\r
141 str r4, [r0, r1] /* store current position in ram */
\r
142 adds r1, r1, #4 /* increment counter */
\r
145 adds r2, r0, r1 /* are we at the final position? */
\r
146 cmp r2, r3 /* ... */
\r
147 bcc CopyDataInit /* nope, continue */
\r
149 /* Fill zero areas */
\r
150 ldr r2, =_sbss /* r2 holds the start address */
\r
151 ldr r5, =_ebss /* r5 holds the end address */
\r
154 ldr r2, =_sstack /* r2 holds the start address */
\r
155 ldr r5, =_estack /* r5 holds the end address */
\r
158 /* Call the application's entry point.*/
\r
164 /* Zero fill the bss segment. */
\r
174 .size Reset_Handler, .-Reset_Handler
\r
179 /******************************************************************************
\r
180 * Interrupt and exception vectors. Vectors start at addr 0x0.
\r
181 ******************************************************************************/
\r
182 .section .int_vecs,"ax",%progbits
\r
183 .extern Irq_Handler
\r
184 .extern Svc_Handler
\r
185 .extern Data_Exc_Handler
\r
186 .extern Prefetch_Exc_Handler
\r
189 /* This is the reset handler. Since the CPU is in ARM mode when this instruction is executed
\r
190 it has to be hard coded (otherwise it will compile wrong).
\r
191 Instruction branches to address 0x22 while changing instruction mode to THUMB. */
\r
194 b Dummy_Irq /* Undefined instruction exception */
\r
195 b Dummy_Irq /* SVC */
\r
196 b Prefetch_Exc_Handler /* Prefetch exception */
\r
197 b Data_Exc_Handler /* Data exception */
\r
198 b Dummy_Irq /* Reserved */
\r
199 b Irq_Handler /* Ordinary interrupts (IRQ) */
\r
200 b Dummy_Irq /* Fast interrupts (FIR) */
\r
203 b Reset_Handler /* Branch to the real reset handler. */
\r