1 /* -------------------------------- Arctic Core ------------------------------
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2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
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4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
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6 * This source code is free software; you can redistribute it and/or modify it
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7 * under the terms of the GNU General Public License version 2 as published by the
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8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
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10 * This program is distributed in the hope that it will be useful, but
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11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 * -------------------------------- Arctic Core ------------------------------*/
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19 #include "Std_Types.h"
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22 #if defined(USE_DEM)
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25 #include "mpc55xx.h"
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31 //#define USE_LDEBUG_PRINTF 1
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34 #define SYSCLOCK_SELECT_PLL 0x2
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36 #if defined(CFG_MPC5567)
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37 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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38 ( (_extal) * ((_emfd)+4) / (((_eprediv)+1)*(1<<(_erfd))) )
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39 #elif defined(CFG_MPC5606S)
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40 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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41 ( (_extal)*(_emfd) / ((_eprediv+1)*(2<<(_erfd))) )
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43 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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44 ( (_extal) * ((_emfd)+16) / (((_eprediv)+1)*((_erfd)+1)) )
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47 typedef void (*vfunc_t)();
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49 /* Function declarations. */
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50 static void Mcu_ConfigureFlash(void);
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53 uint32 lossOfLockCnt;
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54 uint32 lossOfClockCnt;
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58 * Type that holds all global data for Mcu
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62 // Set if Mcu_Init() have been called
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65 const Mcu_ConfigType *config;
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66 Mcu_ClockType clockSetting;
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70 /* Development error macros. */
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71 #if ( MCU_DEV_ERROR_DETECT == STD_ON )
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72 #define VALIDATE(_exp,_api,_err ) \
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74 Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
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78 #define VALIDATE_W_RV(_exp,_api,_err,_rv ) \
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80 Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
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84 #define VALIDATE(_exp,_api,_err )
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85 #define VALIDATE_W_RV(_exp,_api,_err,_rv )
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89 Mcu_GlobalType Mcu_Global =
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92 .config = &McuConfigData[0],
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95 //-------------------------------------------------------------------
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97 void Mcu_LossOfLock( void ){
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98 #if defined(USE_DEM)
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99 Dem_ReportErrorStatus(MCU_E_CLOCK_FAILURE, DEM_EVENT_STATUS_FAILED);
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104 * This interrupt may be triggered more than expected.
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105 * If you are going to use this interrupt, see [Freescale Device Errata MPC5510ACE, Rev. 10 APR 2009, errata ID: 6764].
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108 #if defined(CFG_MPC5606S)
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111 Mcu_Global.stats.lossOfLockCnt++;
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113 FMPLL.SYNSR.B.LOLF = 1;
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117 //-------------------------------------------------------------------
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119 void Mcu_LossOfClock( void ){
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120 /* Should report MCU_E_CLOCK_FAILURE with DEM here */
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121 #if defined(CFG_MPC5606S)
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124 Mcu_Global.stats.lossOfClockCnt++;
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126 FMPLL.SYNSR.B.LOCF = 1;
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130 #define SPR_PIR 286
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131 #define SPR_PVR 287
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133 #define CORE_PVR_E200Z1 0x81440000UL
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134 #define CORE_PVR_E200Z0 0x81710000UL
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135 #define CORE_PVR_E200Z3 0x81120000UL
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136 #define CORE_PVR_E200Z6 0x81170000UL
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137 #define CORE_PVR_E200Z65 0x81150000UL /* Is actually a 5668 */
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138 #define CORE_PVR_E200Z0H 0x817F0000UL
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150 const cpu_info_t cpu_info_list[] = {
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151 #if defined(CFG_MPC5516)
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154 .pvr = CORE_PVR_E200Z1,
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158 .pvr = CORE_PVR_E200Z0,
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160 #elif defined(CFG_MPC5567)
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163 .pvr = CORE_PVR_E200Z6,
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165 #elif defined(CFG_MPC5633)
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168 .pvr = CORE_PVR_E200Z3,
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170 #elif defined(CFG_MPC5606S)
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172 .name = "MPC5606S",
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173 .pvr = CORE_PVR_E200Z0H,
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175 #elif defined(CFG_MPC5668)
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178 .pvr = CORE_PVR_E200Z65,
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182 .pvr = CORE_PVR_E200Z0,
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187 const core_info_t core_info_list[] = {
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188 #if defined(CFG_MPC5516)
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190 .name = "CORE_E200Z1",
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191 .pvr = CORE_PVR_E200Z1,
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194 .name = "CORE_E200Z1",
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195 .pvr = CORE_PVR_E200Z1,
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197 #elif defined(CFG_MPC5567)
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199 .name = "CORE_E200Z6",
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200 .pvr = CORE_PVR_E200Z6,
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202 #elif defined(CFG_MPC5633)
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204 .name = "CORE_E200Z3",
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205 .pvr = CORE_PVR_E200Z3,
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207 #elif defined(CFG_MPC5606S)
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209 .name = "MPC5606S",
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210 .pvr = CORE_PVR_E200Z0H,
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212 #elif defined(CFG_MPC5668)
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214 .name = "CORE_E200Z65",
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215 .pvr = CORE_PVR_E200Z65,
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218 .name = "CORE_E200Z0",
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219 .pvr = CORE_PVR_E200Z1,
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225 #if !defined(ARRAY_SIZE)
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226 #define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))
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229 static const cpu_info_t *Mcu_IdentifyCpu(uint32 pvr)
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233 for (i = 0; i < ARRAY_SIZE(cpu_info_list); i++) {
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234 if (cpu_info_list[i].pvr == pvr) {
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235 return &cpu_info_list[i];
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242 static const core_info_t *Mcu_IdentifyCore(uint32 pvr)
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246 for (i = 0; i < ARRAY_SIZE(core_info_list); i++) {
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247 if (core_info_list[i].pvr == pvr) {
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248 return &core_info_list[i];
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255 static uint32 Mcu_CheckCpu( void ) {
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258 const cpu_info_t *cpuType;
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259 const core_info_t *coreType;
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261 // We have to registers to read here, PIR and PVR
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262 // pir = get_spr(SPR_PIR);
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263 pvr = get_spr(SPR_PVR);
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265 cpuType = Mcu_IdentifyCpu(pvr);
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266 coreType = Mcu_IdentifyCore(pvr);
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268 if( (cpuType == NULL) || (coreType == NULL) ) {
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273 //DEBUG(DEBUG_HIGH,"/drivers/mcu: Cpu: %s( 0x%08x )\n",cpuType->name,pvr);
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274 //DEBUG(DEBUG_HIGH,"/drivers/mcu: Core: %s( 0x%08x )\n",coreType->name,pvr);
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279 //-------------------------------------------------------------------
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281 void Mcu_Init(const Mcu_ConfigType *configPtr)
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283 VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );
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285 #if defined(CFG_MPC5606S)
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286 /* Disable watchdog. Watchdog is enabled default after reset.*/
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287 SWT.SR.R = 0x0000c520; /* Write keys to clear soft lock bit */
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288 SWT.SR.R = 0x0000d928;
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289 SWT.CR.R = 0x8000010A; /* Disable watchdog */
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290 #if defined(USE_WDG)
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291 SWT.TO.R = 0xfa00; /* set the timout to 500ms */
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292 SWT.CR.R = 0x8000011B; /* enable watchdog */
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296 if( !SIMULATOR() ) {
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300 memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));
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303 Mcu_ConfigureFlash();
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305 Mcu_Global.config = configPtr;
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307 #if defined(CFG_MPC5606S)
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308 /* Enable DRUN, RUN0, SAFE, RESET modes */
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309 ME.MER.R = 0x0000001D;
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312 Mcu_Global.initRun = 1;
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314 if( Mcu_Global.config->McuClockSrcFailureNotification == TRUE ) {
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315 #if defined(CFG_MPC5606S)
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318 ISR_INSTALL_ISR1("LossOfLock", Mcu_LossOfLock, PLL_SYNSR_LOLF, 10 , 0 );
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319 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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320 FMPLL.ESYNCR2.B.LOLIRQ = 1;
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321 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
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322 FMPLL.SYNCR.B.LOLIRQ = 1;
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324 ISR_INSTALL_ISR1("LossOfClock", Mcu_LossOfClock, PLL_SYNSR_LOLF, 10 , 0 );
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325 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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326 FMPLL.ESYNCR2.B.LOCIRQ = 1;
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327 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
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328 FMPLL.SYNCR.B.LOCIRQ = 1;
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334 //-------------------------------------------------------------------
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338 Mcu_Global.initRun = FALSE; // Very simple Deinit. Should we do more?
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341 //-------------------------------------------------------------------
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343 Std_ReturnType Mcu_InitRamSection(const Mcu_RamSectionType RamSection)
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345 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );
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346 VALIDATE_W_RV( ( RamSection <= Mcu_Global.config->McuRamSectors ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_PARAM_RAMSECTION, E_NOT_OK );
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348 /* NOT SUPPORTED, reason: no support for external RAM */
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353 //-------------------------------------------------------------------
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355 Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)
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357 Mcu_ClockSettingConfigType *clockSettingsPtr;
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358 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITCLOCK_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );
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359 VALIDATE_W_RV( ( ClockSetting < Mcu_Global.config->McuClockSettings ), MCU_INITCLOCK_SERVICE_ID, MCU_E_PARAM_CLOCK, E_NOT_OK );
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361 Mcu_Global.clockSetting = ClockSetting;
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362 clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];
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364 // TODO: find out if the 5554 really works like the 5516 here
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365 // All three (16, 54, 67) used to run the same code here though, so i'm sticking it with 5516
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366 #if defined(CFG_MPC5516) || defined(CFG_MPC5554) || defined(CFG_MPC5668)
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368 * Fsys - System frequency ( CPU + all periperals? )
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370 * Fsys = EXTAL_FREQ *( (emfd+16) / ( (eprediv+1) * ( erfd+1 )) ) )
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373 assert((clockSettingsPtr->Pll2>=32) && (clockSettingsPtr->Pll2<=132));
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374 assert( (clockSettingsPtr->Pll1 != 6) &&
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375 (clockSettingsPtr->Pll1 != 8) &&
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376 (clockSettingsPtr->Pll1 < 10) );
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377 assert( clockSettingsPtr->Pll3 & 1); // Must be odd
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378 #elif defined(CFG_MPC5567)
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379 /* 5567 clock info:
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380 * Fsys = EXTAL_FREQ *( (emfd+4) / ( (eprediv+1) * ( 2^erfd )) ) )
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383 assert(clockSettingsPtr->Pll2 < 16);
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384 assert(clockSettingsPtr->Pll1 <= 4);
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385 assert(clockSettingsPtr->Pll3 < 8);
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388 #if defined(USE_LDEBUG_PRINTF)
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390 uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
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393 f_sys = CALC_SYSTEM_CLOCK( extal,
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394 clockSettingsPtr->Pll2,
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395 clockSettingsPtr->Pll1,
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396 clockSettingsPtr->Pll3 );
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398 //DEBUG(DEBUG_HIGH,"/drivers/mcu: F_sys will be:%08d Hz\n",f_sys);
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402 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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404 // set post divider to next valid value to ensure that an overshoot during lock phase
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405 // won't result in a too high freq
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406 FMPLL.ESYNCR2.B.ERFD = (clockSettingsPtr->Pll3 + 1) | 1;
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408 // External crystal PLL mode.
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409 FMPLL.ESYNCR1.B.CLKCFG = 7; //TODO: Hur ställa detta för 5567?
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411 // Write pll parameters.
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412 FMPLL.ESYNCR1.B.EPREDIV = clockSettingsPtr->Pll1;
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413 FMPLL.ESYNCR1.B.EMFD = clockSettingsPtr->Pll2;
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415 while(FMPLL.SYNSR.B.LOCK != 1) {};
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417 FMPLL.ESYNCR2.B.ERFD = clockSettingsPtr->Pll3;
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418 // Connect SYSCLK to FMPLL
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419 SIU.SYSCLK.B.SYSCLKSEL = SYSCLOCK_SELECT_PLL;
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421 #elif defined(CFG_MPC5606S)
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422 // Write pll parameters.
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423 CGM.FMPLL[0].CR.B.IDF = clockSettingsPtr->Pll1;
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424 CGM.FMPLL[0].CR.B.NDIV = clockSettingsPtr->Pll2;
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425 CGM.FMPLL[0].CR.B.ODF = clockSettingsPtr->Pll3;
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427 /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */
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428 ME.RUN[0].R = 0x001F0074;
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429 /* Peri. Cfg. 1 settings: only run in RUN0 mode */
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430 ME.RUNPC[1].R = 0x00000010;
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431 /* MPC56xxB/S: select ME.RUNPC[1] */
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432 ME.PCTL[68].R = 0x01; //SIUL control
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433 ME.PCTL[91].R = 0x01; //RTC/API control
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434 ME.PCTL[92].R = 0x01; //PIT_RTI control
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435 ME.PCTL[72].R = 0x01; //eMIOS0 control
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436 ME.PCTL[73].R = 0x01; //eMIOS1 control
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437 ME.PCTL[16].R = 0x01; //FlexCAN0 control
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438 ME.PCTL[17].R = 0x01; //FlexCAN1 control
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439 ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */
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440 ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */
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441 ME.PCTL[32].R = 0x01; //ADC0 control
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442 ME.PCTL[23].R = 0x01; //DMAMUX control
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443 ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */
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444 ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */
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445 /* Mode Transition to enter RUN0 mode: */
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446 /* Enter RUN0 Mode & Key */
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447 ME.MCTL.R = 0x40005AF0;
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448 /* Enter RUN0 Mode & Inverted Key */
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449 ME.MCTL.R = 0x4000A50F;
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451 /* Wait for mode transition to complete */
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452 while (ME.GS.B.S_MTRANS) {}
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453 /* Verify RUN0 is the current mode */
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454 while(ME.GS.B.S_CURRENTMODE != 4) {}
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456 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
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457 // Partially following the steps in MPC5567 RM..
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458 FMPLL.SYNCR.B.DEPTH = 0;
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459 FMPLL.SYNCR.B.LOLRE = 0;
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460 FMPLL.SYNCR.B.LOLIRQ = 0;
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462 FMPLL.SYNCR.B.PREDIV = clockSettingsPtr->Pll1;
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463 FMPLL.SYNCR.B.MFD = clockSettingsPtr->Pll2;
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464 FMPLL.SYNCR.B.RFD = clockSettingsPtr->Pll3;
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466 // Wait for PLL to sync.
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467 while (Mcu_GetPllStatus() != MCU_PLL_LOCKED) ;
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469 FMPLL.SYNCR.B.LOLIRQ = 1;
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475 //-------------------------------------------------------------------
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477 void Mcu_DistributePllClock(void)
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479 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );
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480 #if defined(CFG_MPC5606S)
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481 VALIDATE( ( CGM.FMPLL[0].CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
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483 VALIDATE( ( FMPLL.SYNSR.B.LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
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485 /* NOT IMPLEMENTED due to pointless function on this hardware */
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489 //-------------------------------------------------------------------
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491 Mcu_PllStatusType Mcu_GetPllStatus(void)
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493 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );
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494 Mcu_PllStatusType rv;
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498 #if defined(CFG_MPC5606S)
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499 if ( !CGM.FMPLL[0].CR.B.S_LOCK )
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501 rv = MCU_PLL_UNLOCKED;
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504 rv = MCU_PLL_LOCKED;
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507 if ( !FMPLL.SYNSR.B.LOCK )
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509 rv = MCU_PLL_UNLOCKED;
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512 rv = MCU_PLL_LOCKED;
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518 /* We are running on instruction set simulator. PLL is then always in sync... */
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519 rv = MCU_PLL_LOCKED;
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525 //-------------------------------------------------------------------
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527 Mcu_ResetType Mcu_GetResetReason(void)
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531 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );
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533 #if defined(CFG_MPC5606S)
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534 if( RGM.FES.B.F_SOFT ) {
\r
536 } else if( RGM.DES.B.F_SWT ) {
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537 rv = MCU_WATCHDOG_RESET;
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538 } else if( RGM.DES.B.F_POR ) {
\r
539 rv = MCU_POWER_ON_RESET;
\r
541 rv = MCU_RESET_UNDEFINED;
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544 if( SIU.RSR.B.SSRS ) {
\r
546 } else if( SIU.RSR.B.WDRS ) {
\r
547 rv = MCU_WATCHDOG_RESET;
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548 } else if( SIU.RSR.B.PORS || SIU.RSR.B.ERS ) {
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549 rv = MCU_POWER_ON_RESET;
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551 rv = MCU_RESET_UNDEFINED;
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558 //-------------------------------------------------------------------
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560 Mcu_RawResetType Mcu_GetResetRawValue(void)
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562 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_GETRESETRAWVALUE_UNINIT_RV );
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564 if( !Mcu_Global.initRun ) {
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565 return MCU_GETRESETRAWVALUE_UNINIT_RV;
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568 #if defined(CFG_MPC5606S)
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579 //-------------------------------------------------------------------
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581 #if ( MCU_PERFORM_RESET_API == STD_ON )
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582 void Mcu_PerformReset(void)
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584 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_PERFORMRESET_SERVICE_ID, MCU_E_UNINIT );
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587 #if defined(CFG_MPC5606S)
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588 ME.MCTL.R = 0x00005AF0;
\r
589 ME.MCTL.R = 0x0000A50F;
\r
591 while (ME.GS.B.S_MTRANS) {}
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592 while(ME.GS.B.S_CURRENTMODE != 0) {}
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594 SIU.SRCR.B.SSR = 1;
\r
600 //-------------------------------------------------------------------
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602 void Mcu_SetMode(const Mcu_ModeType McuMode)
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604 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );
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605 // VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );
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608 /* NOT SUPPORTED */
\r
611 //-------------------------------------------------------------------
\r
614 * Get the system clock in Hz. It calculates the clock from the
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615 * different register settings in HW.
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617 uint32_t McuE_GetSystemClock(void)
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620 * System clock calculation
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622 * 5516 - f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));
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623 * 5567 - f_sys = extal * (emfd+4) / ( (eprediv+1) * ( 2^erfd ));
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624 * 563x - We run in legacy mode = 5567
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625 * 5606s - f_sys = extal * emfd / ((eprediv+1)*(2<<(erfd)));
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627 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
628 uint32_t eprediv = FMPLL.ESYNCR1.B.EPREDIV;
\r
629 uint32_t emfd = FMPLL.ESYNCR1.B.EMFD;
\r
630 uint32_t erfd = FMPLL.ESYNCR2.B.ERFD;
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631 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567) || defined(CFG_MPC5633)
\r
632 uint32_t eprediv = FMPLL.SYNCR.B.PREDIV;
\r
633 uint32_t emfd = FMPLL.SYNCR.B.MFD;
\r
634 uint32_t erfd = FMPLL.SYNCR.B.RFD;
\r
635 #elif defined(CFG_MPC5606S)
\r
636 uint32_t eprediv = CGM.FMPLL[0].CR.B.IDF;
\r
637 uint32_t emfd = CGM.FMPLL[0].CR.B.NDIV;
\r
638 uint32_t erfd = CGM.FMPLL[0].CR.B.ODF;
\r
642 uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
\r
644 f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);
\r
649 #if defined(CFG_MPC5668)
\r
650 uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type) {
\r
651 uint32_t sysClock = McuE_GetSystemClock();
\r
652 vuint32_t prescaler;
\r
656 case PERIPHERAL_CLOCK_FLEXCAN_A:
\r
657 case PERIPHERAL_CLOCK_FLEXCAN_B:
\r
658 case PERIPHERAL_CLOCK_FLEXCAN_C:
\r
659 case PERIPHERAL_CLOCK_FLEXCAN_D:
\r
660 case PERIPHERAL_CLOCK_FLEXCAN_E:
\r
661 case PERIPHERAL_CLOCK_FLEXCAN_F:
\r
662 case PERIPHERAL_CLOCK_DSPI_A:
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663 case PERIPHERAL_CLOCK_DSPI_B:
\r
664 case PERIPHERAL_CLOCK_DSPI_C:
\r
665 case PERIPHERAL_CLOCK_DSPI_D:
\r
666 prescaler = SIU.SYSCLK.B.LPCLKDIV1;
\r
668 case PERIPHERAL_CLOCK_ESCI_A:
\r
669 case PERIPHERAL_CLOCK_ESCI_B:
\r
670 case PERIPHERAL_CLOCK_ESCI_C:
\r
671 case PERIPHERAL_CLOCK_ESCI_D:
\r
672 case PERIPHERAL_CLOCK_ESCI_E:
\r
673 case PERIPHERAL_CLOCK_ESCI_F:
\r
674 case PERIPHERAL_CLOCK_IIC_A:
\r
675 case PERIPHERAL_CLOCK_IIC_B:
\r
676 prescaler = SIU.SYSCLK.B.LPCLKDIV0;
\r
678 case PERIPHERAL_CLOCK_ADC_A:
\r
679 prescaler = SIU.SYSCLK.B.LPCLKDIV2;
\r
681 case PERIPHERAL_CLOCK_EMIOS:
\r
682 prescaler = SIU.SYSCLK.B.LPCLKDIV3;
\r
689 return sysClock/(1<<prescaler);
\r
696 * Get the peripheral clock in Hz for a specific device
\r
698 uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)
\r
700 #if defined(CFG_MPC5567)
\r
701 // No peripheral dividers on 5567.
\r
702 return McuE_GetSystemClock();
\r
704 uint32_t sysClock = McuE_GetSystemClock();
\r
705 vuint32_t prescaler;
\r
707 // See table 3.1, section 3.4.5 Peripheral Clock dividers
\r
710 case PERIPHERAL_CLOCK_FLEXCAN_A:
\r
711 case PERIPHERAL_CLOCK_DSPI_A:
\r
712 #if defined(CFG_MPC5516)
\r
713 prescaler = SIU.SYSCLK.B.LPCLKDIV0;
\r
715 #elif defined(CFG_MPC5606S)
\r
716 prescaler = CGM.SC_DC[1].B.DIV;
\r
720 case PERIPHERAL_CLOCK_PIT:
\r
721 case PERIPHERAL_CLOCK_ESCI_A:
\r
722 case PERIPHERAL_CLOCK_IIC_A:
\r
723 #if defined(CFG_MPC5516)
\r
724 prescaler = SIU.SYSCLK.B.LPCLKDIV1;
\r
728 case PERIPHERAL_CLOCK_FLEXCAN_B:
\r
729 case PERIPHERAL_CLOCK_FLEXCAN_C:
\r
730 case PERIPHERAL_CLOCK_FLEXCAN_D:
\r
731 case PERIPHERAL_CLOCK_FLEXCAN_E:
\r
732 case PERIPHERAL_CLOCK_FLEXCAN_F:
\r
733 #if defined(CFG_MPC5516)
\r
734 prescaler = SIU.SYSCLK.B.LPCLKDIV2;
\r
736 #elif defined(CFG_MPC5606S)
\r
737 prescaler = CGM.SC_DC[1].B.DIV;
\r
741 case PERIPHERAL_CLOCK_DSPI_B:
\r
742 case PERIPHERAL_CLOCK_DSPI_C:
\r
743 case PERIPHERAL_CLOCK_DSPI_D:
\r
744 #if defined(CFG_MPC5516)
\r
745 prescaler = SIU.SYSCLK.B.LPCLKDIV3;
\r
749 case PERIPHERAL_CLOCK_ESCI_B:
\r
750 case PERIPHERAL_CLOCK_ESCI_C:
\r
751 case PERIPHERAL_CLOCK_ESCI_D:
\r
752 case PERIPHERAL_CLOCK_ESCI_E:
\r
753 case PERIPHERAL_CLOCK_ESCI_F:
\r
754 case PERIPHERAL_CLOCK_ESCI_G:
\r
755 case PERIPHERAL_CLOCK_ESCI_H:
\r
756 #if defined(CFG_MPC5516)
\r
757 prescaler = SIU.SYSCLK.B.LPCLKDIV4;
\r
761 #if defined(CFG_MPC5606S)
\r
762 case PERIPHERAL_CLOCK_LIN_A:
\r
763 case PERIPHERAL_CLOCK_LIN_B:
\r
764 prescaler = CGM.SC_DC[0].B.DIV;
\r
766 case PERIPHERAL_CLOCK_EMIOS_0:
\r
767 prescaler = CGM.SC_DC[2].B.DIV;
\r
769 case PERIPHERAL_CLOCK_EMIOS_1:
\r
770 prescaler = CGM.SC_DC[2].B.DIV;
\r
773 case PERIPHERAL_CLOCK_EMIOS:
\r
774 #if defined(CFG_MPC5516)
\r
775 prescaler = SIU.SYSCLK.B.LPCLKDIV5;
\r
780 case PERIPHERAL_CLOCK_MLB:
\r
781 #if defined(CFG_MPC5516)
\r
782 prescaler = SIU.SYSCLK.B.LPCLKDIV6;
\r
791 return sysClock/(1<<prescaler);
\r
797 * Function to setup the internal flash for optimal performance
\r
800 static void Mcu_ConfigureFlash(void)
\r
802 /* These flash settings increases the CPU performance of 7 times compared
\r
803 to reset default settings!! */
\r
805 #if defined(CFG_MPC5516)
\r
806 /* Disable pipelined reads when flash options are changed. */
\r
807 FLASH.MCR.B.PRD = 1;
\r
809 /* Enable master prefetch for e200z1 and eDMA. */
\r
810 FLASH.PFCRP0.B.M0PFE = 1;
\r
811 FLASH.PFCRP0.B.M2PFE = 1;
\r
813 /* Address pipelining control. Must be set to the same value as RWSC. */
\r
814 FLASH.PFCRP0.B.APC = 2;
\r
815 FLASH.PFCRP0.B.RWSC = 2;
\r
817 /* Write wait states. */
\r
818 FLASH.PFCRP0.B.WWSC = 1;
\r
820 /* Enable data prefetch. */
\r
821 FLASH.PFCRP0.B.DPFEN = 1;
\r
823 /* Enable instruction prefetch. */
\r
824 FLASH.PFCRP0.B.IPFEN = 1;
\r
826 /* Prefetch algorithm. */
\r
827 /* TODO: Ask Freescale about this option. */
\r
828 FLASH.PFCRP0.B.PFLIM = 2;
\r
830 /* Enable line read buffers. */
\r
831 FLASH.PFCRP0.B.BFEN = 1;
\r
833 /* Enable pipelined reads again. */
\r
834 FLASH.MCR.B.PRD = 0;
\r
835 #elif defined(CFG_MPC5668)
\r
836 /* Check values from cookbook and MPC5668x Microcontroller Data Sheet */
\r
838 /* Should probably trim this values */
\r
839 const typeof(FLASH.PFCRP0.B) val = {.M0PFE = 1, .M2PFE=1, .APC=3,
\r
840 .RWSC=3, .WWSC =1, .DPFEN =1, .IPFEN = 1, .PFLIM =2,
\r
842 FLASH.PFCRP0.B = val;
\r
844 /* Enable pipelined reads again. */
\r
845 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
\r
846 //TODO: Lägg till flash för mpc5554 &67
\r