1 /* -------------------------------- Arctic Core ------------------------------
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2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
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4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
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6 * This source code is free software; you can redistribute it and/or modify it
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7 * under the terms of the GNU General Public License version 2 as published by the
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8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
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10 * This program is distributed in the hope that it will be useful, but
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11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 * -------------------------------- Arctic Core ------------------------------*/
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17 /* ----------------------------[includes]------------------------------------*/
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20 #include "Std_Types.h"
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23 #if defined(USE_DEM)
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26 #include "mpc55xx.h"
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33 //#define USE_LDEBUG_PRINTF 1
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36 /* ----------------------------[private define]------------------------------*/
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38 #define SYSCLOCK_SELECT_PLL 0x2
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40 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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42 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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43 #define CRP_BASE (0xFFFEC000ul)
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45 #error Please define CRP_BASE
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48 #define CRP_CLKSRC (CRP_BASE+0x0)
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49 #define CRP_RTCSC (CRP_BASE+0x10)
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50 #define CRP_RTCCNT (CRP_BASE+0x14)
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51 /* 40--4F differs ALOT */
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52 #define CRP_Z1VEC (CRP_BASE+0x50)
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53 #define CRP_Z6VEC (CRP_BASE+0x50)
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54 #define CRP_Z0VEC (CRP_BASE+0x54)
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55 #define CRP_RECPTR (CRP_BASE+0x58)
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56 #define CRP_PSCR (CRP_BASE+0x60)
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58 #define xVEC_xVEC(_x)
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59 #define PSCR_SLEEP 0x00008000ul
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60 #define PSCR_SLP12EN 0x00000800ul
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61 #define PCSR_RAMSEL(_x) ((_x)<<8)
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62 #define xVEC_VLE 0x00000001ul
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63 #define xVEC_xRST 0x00000002ul
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65 #define RECPTR_FASTREC 0x00000002ul
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68 #if defined(CFG_VLE)
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69 #define VLE_VAL xVEC_VLE
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74 #if defined(CFG_MPC5516 )
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75 #define RAMSEL_VAL 0x7
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76 #elif defined(CFG_MPC5668)
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77 #define RAMSEL_VAL 0x3
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79 #error Please define RAMSEL_VAL
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85 /* ----------------------------[private macro]-------------------------------*/
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88 #if defined(CFG_MPC5567)
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89 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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90 ( (_extal) * ((_emfd)+4) / (((_eprediv)+1)*(1<<(_erfd))) )
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91 #elif defined(CFG_MPC560X)
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92 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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93 ( (_extal)*(_emfd) / ((_eprediv+1)*(2<<(_erfd))) )
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95 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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96 ( (_extal) * ((_emfd)+16) / (((_eprediv)+1)*((_erfd)+1)) )
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99 /* ----------------------------[private typedef]-----------------------------*/
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102 typedef void (*vfunc_t)();
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105 /* ----------------------------[private function prototypes]-----------------*/
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106 /* ----------------------------[private variables]---------------------------*/
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108 #if defined(CFG_MPC5516)
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109 static uint32 Mcu_SavedHaltFlags;
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111 static uint32 Mcu_SavedHaltFlags[2];
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116 /* ----------------------------[private functions]---------------------------*/
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117 /* ----------------------------[public functions]----------------------------*/
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119 /* Function declarations. */
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120 static void Mcu_ConfigureFlash(void);
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123 uint32 lossOfLockCnt;
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124 uint32 lossOfClockCnt;
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128 * Type that holds all global data for Mcu
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132 // Set if Mcu_Init() have been called
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135 const Mcu_ConfigType *config;
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136 Mcu_ClockType clockSetting;
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140 /* Development error macros. */
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141 #if ( MCU_DEV_ERROR_DETECT == STD_ON )
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142 #define VALIDATE(_exp,_api,_err ) \
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144 Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
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148 #define VALIDATE_W_RV(_exp,_api,_err,_rv ) \
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150 Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
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154 #define VALIDATE(_exp,_api,_err )
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155 #define VALIDATE_W_RV(_exp,_api,_err,_rv )
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159 Mcu_GlobalType Mcu_Global =
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162 .config = &McuConfigData[0],
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165 //-------------------------------------------------------------------
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167 void Mcu_LossOfLock( void ){
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168 #if defined(USE_DEM)
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169 Dem_ReportErrorStatus(MCU_E_CLOCK_FAILURE, DEM_EVENT_STATUS_FAILED);
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174 * This interrupt may be triggered more than expected.
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175 * If you are going to use this interrupt, see [Freescale Device Errata MPC5510ACE, Rev. 10 APR 2009, errata ID: 6764].
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178 #if defined(CFG_MPC560X)
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181 Mcu_Global.stats.lossOfLockCnt++;
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183 FMPLL.SYNSR.B.LOLF = 1;
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187 //-------------------------------------------------------------------
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189 void Mcu_LossOfClock( void ){
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190 /* Should report MCU_E_CLOCK_FAILURE with DEM here */
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191 #if defined(CFG_MPC560X)
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194 Mcu_Global.stats.lossOfClockCnt++;
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196 FMPLL.SYNSR.B.LOCF = 1;
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200 #define SPR_PIR 286
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201 #define SPR_PVR 287
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203 #define CORE_PVR_E200Z1 0x81440000UL
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204 #define CORE_PVR_E200Z0 0x81710000UL
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205 #define CORE_PVR_E200Z3 0x81120000UL
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206 #define CORE_PVR_E200Z6 0x81170000UL
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207 #define CORE_PVR_E200Z65 0x81150000UL /* Is actually a 5668 */
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208 #define CORE_PVR_E200Z0H 0x817F0000UL
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220 const cpu_info_t cpu_info_list[] = {
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221 #if defined(CFG_MPC5516)
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224 .pvr = CORE_PVR_E200Z1,
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228 .pvr = CORE_PVR_E200Z0,
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230 #elif defined(CFG_MPC5567)
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233 .pvr = CORE_PVR_E200Z6,
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235 #elif defined(CFG_MPC5633)
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238 .pvr = CORE_PVR_E200Z3,
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240 #elif defined(CFG_MPC5604B)
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242 .name = "MPC5604B",
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243 .pvr = CORE_PVR_E200Z0H,
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245 #elif defined(CFG_MPC5606B)
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247 .name = "MPC5606B",
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248 .pvr = CORE_PVR_E200Z0H,
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250 #elif defined(CFG_MPC5606S)
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252 .name = "MPC5606S",
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253 .pvr = CORE_PVR_E200Z0H,
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255 #elif defined(CFG_MPC5668)
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258 .pvr = CORE_PVR_E200Z65,
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262 .pvr = CORE_PVR_E200Z0,
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267 const core_info_t core_info_list[] = {
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268 #if defined(CFG_MPC5516)
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270 .name = "CORE_E200Z1",
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271 .pvr = CORE_PVR_E200Z1,
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274 .name = "CORE_E200Z1",
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275 .pvr = CORE_PVR_E200Z1,
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277 #elif defined(CFG_MPC5567)
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279 .name = "CORE_E200Z6",
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280 .pvr = CORE_PVR_E200Z6,
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282 #elif defined(CFG_MPC5633)
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284 .name = "CORE_E200Z3",
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285 .pvr = CORE_PVR_E200Z3,
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287 #elif defined(CFG_MPC5604B)
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289 .name = "MPC5604B",
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290 .pvr = CORE_PVR_E200Z0H,
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292 #elif defined(CFG_MPC5606B)
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294 .name = "MPC5606B",
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295 .pvr = CORE_PVR_E200Z0H,
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297 #elif defined(CFG_MPC5606S)
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299 .name = "MPC5606S",
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300 .pvr = CORE_PVR_E200Z0H,
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302 #elif defined(CFG_MPC5668)
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304 .name = "CORE_E200Z65",
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305 .pvr = CORE_PVR_E200Z65,
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308 .name = "CORE_E200Z0",
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309 .pvr = CORE_PVR_E200Z1,
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315 #if !defined(ARRAY_SIZE)
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316 #define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))
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319 static const cpu_info_t *Mcu_IdentifyCpu(uint32 pvr)
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323 for (i = 0; i < ARRAY_SIZE(cpu_info_list); i++) {
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324 if (cpu_info_list[i].pvr == pvr) {
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325 return &cpu_info_list[i];
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332 static const core_info_t *Mcu_IdentifyCore(uint32 pvr)
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336 for (i = 0; i < ARRAY_SIZE(core_info_list); i++) {
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337 if (core_info_list[i].pvr == pvr) {
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338 return &core_info_list[i];
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345 static uint32 Mcu_CheckCpu( void ) {
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348 const cpu_info_t *cpuType;
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349 const core_info_t *coreType;
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351 // We have to registers to read here, PIR and PVR
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352 // pir = get_spr(SPR_PIR);
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353 pvr = get_spr(SPR_PVR);
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355 cpuType = Mcu_IdentifyCpu(pvr);
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356 coreType = Mcu_IdentifyCore(pvr);
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358 if( (cpuType == NULL) || (coreType == NULL) ) {
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363 //DEBUG(DEBUG_HIGH,"/drivers/mcu: Cpu: %s( 0x%08x )\n",cpuType->name,pvr);
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364 //DEBUG(DEBUG_HIGH,"/drivers/mcu: Core: %s( 0x%08x )\n",coreType->name,pvr);
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369 //-------------------------------------------------------------------
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371 void Mcu_Init(const Mcu_ConfigType *configPtr)
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373 VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );
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375 #if defined(CFG_MPC560X)
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376 /* Disable watchdog. Watchdog is enabled default after reset.*/
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377 SWT.SR.R = 0x0000c520; /* Write keys to clear soft lock bit */
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378 SWT.SR.R = 0x0000d928;
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379 SWT.CR.R = 0x8000010A; /* Disable watchdog */
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380 #if defined(USE_WDG)
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381 SWT.TO.R = 0xfa00; /* set the timout to 500ms */
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382 SWT.CR.R = 0x8000011B; /* enable watchdog */
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386 if( !SIMULATOR() ) {
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390 memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));
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393 Mcu_ConfigureFlash();
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395 Mcu_Global.config = configPtr;
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397 #if defined(CFG_MPC560X)
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398 /* Enable DRUN, RUN0, SAFE, RESET modes */
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399 ME.MER.R = 0x0000001D;
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402 Mcu_Global.initRun = 1;
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404 if( Mcu_Global.config->McuClockSrcFailureNotification == TRUE ) {
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405 #if defined(CFG_MPC560X)
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408 ISR_INSTALL_ISR1("LossOfLock", Mcu_LossOfLock, PLL_SYNSR_LOLF, 10 , 0 );
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409 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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410 FMPLL.ESYNCR2.B.LOLIRQ = 1;
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411 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
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412 FMPLL.SYNCR.B.LOLIRQ = 1;
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414 ISR_INSTALL_ISR1("LossOfClock", Mcu_LossOfClock, PLL_SYNSR_LOLF, 10 , 0 );
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415 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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416 FMPLL.ESYNCR2.B.LOCIRQ = 1;
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417 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
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418 FMPLL.SYNCR.B.LOCIRQ = 1;
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424 //-------------------------------------------------------------------
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428 Mcu_Global.initRun = FALSE; // Very simple Deinit. Should we do more?
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431 //-------------------------------------------------------------------
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433 Std_ReturnType Mcu_InitRamSection(const Mcu_RamSectionType RamSection)
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435 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );
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436 VALIDATE_W_RV( ( RamSection <= Mcu_Global.config->McuRamSectors ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_PARAM_RAMSECTION, E_NOT_OK );
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438 /* NOT SUPPORTED, reason: no support for external RAM */
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443 //-------------------------------------------------------------------
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445 Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)
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447 Mcu_ClockSettingConfigType *clockSettingsPtr;
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448 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITCLOCK_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );
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449 VALIDATE_W_RV( ( ClockSetting < Mcu_Global.config->McuClockSettings ), MCU_INITCLOCK_SERVICE_ID, MCU_E_PARAM_CLOCK, E_NOT_OK );
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451 Mcu_Global.clockSetting = ClockSetting;
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452 clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];
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454 // TODO: find out if the 5554 really works like the 5516 here
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455 // All three (16, 54, 67) used to run the same code here though, so i'm sticking it with 5516
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456 #if defined(CFG_SIMULATOR)
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458 #elif defined(CFG_MPC5516) || defined(CFG_MPC5554) || defined(CFG_MPC5668)
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460 * Fsys - System frequency ( CPU + all periperals? )
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462 * Fsys = EXTAL_FREQ *( (emfd+16) / ( (eprediv+1) * ( erfd+1 )) ) )
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465 assert((clockSettingsPtr->Pll2>=32) && (clockSettingsPtr->Pll2<=132));
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466 assert( (clockSettingsPtr->Pll1 != 6) &&
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467 (clockSettingsPtr->Pll1 != 8) &&
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468 (clockSettingsPtr->Pll1 < 10) );
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469 assert( clockSettingsPtr->Pll3 & 1); // Must be odd
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470 #elif defined(CFG_MPC5567)
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471 /* 5567 clock info:
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472 * Fsys = EXTAL_FREQ *( (emfd+4) / ( (eprediv+1) * ( 2^erfd )) ) )
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475 assert(clockSettingsPtr->Pll2 < 16);
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476 assert(clockSettingsPtr->Pll1 <= 4);
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477 assert(clockSettingsPtr->Pll3 < 8);
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480 #if defined(USE_LDEBUG_PRINTF)
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482 uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
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485 f_sys = CALC_SYSTEM_CLOCK( extal,
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486 clockSettingsPtr->Pll2,
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487 clockSettingsPtr->Pll1,
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488 clockSettingsPtr->Pll3 );
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490 //DEBUG(DEBUG_HIGH,"/drivers/mcu: F_sys will be:%08d Hz\n",f_sys);
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494 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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496 // set post divider to next valid value to ensure that an overshoot during lock phase
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497 // won't result in a too high freq
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498 FMPLL.ESYNCR2.B.ERFD = (clockSettingsPtr->Pll3 + 1) | 1;
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500 // External crystal PLL mode.
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501 FMPLL.ESYNCR1.B.CLKCFG = 7; //TODO: Hur ställa detta för 5567?
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503 // Write pll parameters.
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504 FMPLL.ESYNCR1.B.EPREDIV = clockSettingsPtr->Pll1;
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505 FMPLL.ESYNCR1.B.EMFD = clockSettingsPtr->Pll2;
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507 while(FMPLL.SYNSR.B.LOCK != 1) {};
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509 FMPLL.ESYNCR2.B.ERFD = clockSettingsPtr->Pll3;
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510 // Connect SYSCLK to FMPLL
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511 SIU.SYSCLK.B.SYSCLKSEL = SYSCLOCK_SELECT_PLL;
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512 #elif defined(CFG_MPC5604B) || defined(CFG_MPC5606B)
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513 // Write pll parameters.
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514 CGM.FMPLL_CR.B.IDF = clockSettingsPtr->Pll1;
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515 CGM.FMPLL_CR.B.NDIV = clockSettingsPtr->Pll2;
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516 CGM.FMPLL_CR.B.ODF = clockSettingsPtr->Pll3;
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518 /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */
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519 ME.RUN[0].R = 0x001F0074;
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520 /* Peri. Cfg. 1 settings: only run in RUN0 mode */
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521 ME.RUNPC[1].R = 0x00000010;
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522 /* MPC56xxB/S: select ME.RUNPC[1] */
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523 ME.PCTL[68].R = 0x01; //SIUL control
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524 ME.PCTL[91].R = 0x01; //RTC/API control
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525 ME.PCTL[92].R = 0x01; //PIT_RTI control
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526 ME.PCTL[72].R = 0x01; //eMIOS0 control
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527 ME.PCTL[73].R = 0x01; //eMIOS1 control
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528 ME.PCTL[16].R = 0x01; //FlexCAN0 control
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529 ME.PCTL[17].R = 0x01; //FlexCAN1 control
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530 ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */
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531 ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */
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532 ME.PCTL[32].R = 0x01; //ADC0 control
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533 #if defined(CFG_MPC5606B)
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534 ME.PCTL[33].R = 0x01; //ADC1 control
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536 ME.PCTL[23].R = 0x01; //DMAMUX control
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537 ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */
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538 ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */
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539 /* Mode Transition to enter RUN0 mode: */
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540 /* Enter RUN0 Mode & Key */
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541 ME.MCTL.R = 0x40005AF0;
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542 /* Enter RUN0 Mode & Inverted Key */
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543 ME.MCTL.R = 0x4000A50F;
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545 /* Wait for mode transition to complete */
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546 while (ME.GS.B.S_MTRANS) {}
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547 /* Verify RUN0 is the current mode */
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548 while(ME.GS.B.S_CURRENTMODE != 4) {}
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550 CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */
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551 CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */
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552 CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */
\r
554 SIU.PSMI[0].R = 0x01; /* CAN1RX on PCR43 */
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555 SIU.PSMI[6].R = 0x01; /* CS0/DSPI_0 on PCR15 */
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557 #elif defined(CFG_MPC5606S)
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558 // Write pll parameters.
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559 CGM.FMPLL[0].CR.B.IDF = clockSettingsPtr->Pll1;
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560 CGM.FMPLL[0].CR.B.NDIV = clockSettingsPtr->Pll2;
\r
561 CGM.FMPLL[0].CR.B.ODF = clockSettingsPtr->Pll3;
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563 /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */
\r
564 ME.RUN[0].R = 0x001F0074;
\r
565 /* Peri. Cfg. 1 settings: only run in RUN0 mode */
\r
566 ME.RUNPC[1].R = 0x00000010;
\r
567 /* MPC56xxB/S: select ME.RUNPC[1] */
\r
568 ME.PCTL[68].R = 0x01; //SIUL control
\r
569 ME.PCTL[91].R = 0x01; //RTC/API control
\r
570 ME.PCTL[92].R = 0x01; //PIT_RTI control
\r
571 ME.PCTL[72].R = 0x01; //eMIOS0 control
\r
572 ME.PCTL[73].R = 0x01; //eMIOS1 control
\r
573 ME.PCTL[16].R = 0x01; //FlexCAN0 control
\r
574 ME.PCTL[17].R = 0x01; //FlexCAN1 control
\r
575 ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */
\r
576 ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */
\r
577 ME.PCTL[32].R = 0x01; //ADC0 control
\r
578 ME.PCTL[23].R = 0x01; //DMAMUX control
\r
579 ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
580 ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
581 /* Mode Transition to enter RUN0 mode: */
\r
582 /* Enter RUN0 Mode & Key */
\r
583 ME.MCTL.R = 0x40005AF0;
\r
584 /* Enter RUN0 Mode & Inverted Key */
\r
585 ME.MCTL.R = 0x4000A50F;
\r
587 /* Wait for mode transition to complete */
\r
588 while (ME.GS.B.S_MTRANS) {}
\r
589 /* Verify RUN0 is the current mode */
\r
590 while(ME.GS.B.S_CURRENTMODE != 4) {}
\r
592 CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */
\r
593 CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */
\r
594 CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */
\r
596 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
\r
597 // Partially following the steps in MPC5567 RM..
\r
598 FMPLL.SYNCR.B.DEPTH = 0;
\r
599 FMPLL.SYNCR.B.LOLRE = 0;
\r
600 FMPLL.SYNCR.B.LOLIRQ = 0;
\r
602 FMPLL.SYNCR.B.PREDIV = clockSettingsPtr->Pll1;
\r
603 FMPLL.SYNCR.B.MFD = clockSettingsPtr->Pll2;
\r
604 FMPLL.SYNCR.B.RFD = clockSettingsPtr->Pll3;
\r
606 // Wait for PLL to sync.
\r
607 while (Mcu_GetPllStatus() != MCU_PLL_LOCKED) ;
\r
609 FMPLL.SYNCR.B.LOLIRQ = 1;
\r
615 //-------------------------------------------------------------------
\r
617 void Mcu_DistributePllClock(void)
\r
619 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );
\r
620 #if defined(CFG_MPC560XB)
\r
621 VALIDATE( ( CGM.FMPLL_CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
622 #elif defined(CFG_MPC5606S)
\r
623 VALIDATE( ( CGM.FMPLL[0].CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
625 VALIDATE( ( FMPLL.SYNSR.B.LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
627 /* NOT IMPLEMENTED due to pointless function on this hardware */
\r
631 //-------------------------------------------------------------------
\r
633 Mcu_PllStatusType Mcu_GetPllStatus(void)
\r
635 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );
\r
636 Mcu_PllStatusType rv;
\r
640 #if defined(CFG_MPC560XB)
\r
641 if ( !CGM.FMPLL_CR.B.S_LOCK )
\r
643 rv = MCU_PLL_UNLOCKED;
\r
646 rv = MCU_PLL_LOCKED;
\r
648 #elif defined(CFG_MPC5606S)
\r
649 if ( !CGM.FMPLL[0].CR.B.S_LOCK )
\r
651 rv = MCU_PLL_UNLOCKED;
\r
654 rv = MCU_PLL_LOCKED;
\r
657 if ( !FMPLL.SYNSR.B.LOCK )
\r
659 rv = MCU_PLL_UNLOCKED;
\r
662 rv = MCU_PLL_LOCKED;
\r
668 /* We are running on instruction set simulator. PLL is then always in sync... */
\r
669 rv = MCU_PLL_LOCKED;
\r
675 //-------------------------------------------------------------------
\r
677 Mcu_ResetType Mcu_GetResetReason(void)
\r
681 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );
\r
683 #if defined(CFG_MPC560X)
\r
684 if( RGM.FES.B.F_SOFT ) {
\r
686 } else if( RGM.DES.B.F_SWT ) {
\r
687 rv = MCU_WATCHDOG_RESET;
\r
688 } else if( RGM.DES.B.F_POR ) {
\r
689 rv = MCU_POWER_ON_RESET;
\r
691 rv = MCU_RESET_UNDEFINED;
\r
694 if( SIU.RSR.B.SSRS ) {
\r
696 } else if( SIU.RSR.B.WDRS ) {
\r
697 rv = MCU_WATCHDOG_RESET;
\r
698 } else if( SIU.RSR.B.PORS || SIU.RSR.B.ERS ) {
\r
699 rv = MCU_POWER_ON_RESET;
\r
701 rv = MCU_RESET_UNDEFINED;
\r
708 //-------------------------------------------------------------------
\r
710 Mcu_RawResetType Mcu_GetResetRawValue(void)
\r
712 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_GETRESETRAWVALUE_UNINIT_RV );
\r
714 if( !Mcu_Global.initRun ) {
\r
715 return MCU_GETRESETRAWVALUE_UNINIT_RV;
\r
718 #if defined(CFG_MPC560X)
\r
729 //-------------------------------------------------------------------
\r
731 #if ( MCU_PERFORM_RESET_API == STD_ON )
\r
732 void Mcu_PerformReset(void)
\r
734 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_PERFORMRESET_SERVICE_ID, MCU_E_UNINIT );
\r
737 #if defined(CFG_MPC560X)
\r
738 ME.MCTL.R = 0x00005AF0;
\r
739 ME.MCTL.R = 0x0000A50F;
\r
741 while (ME.GS.B.S_MTRANS) {}
\r
742 while(ME.GS.B.S_CURRENTMODE != 0) {}
\r
744 SIU.SRCR.B.SSR = 1;
\r
750 //-------------------------------------------------------------------
\r
752 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
756 * Application Notes!
\r
757 * - AN3584, "MPC5510 Family Low Power Features"
\r
758 * Since it's not complete also check MPC5668
\r
759 * - AN4150 , "Using Sleep Mode on the MPC5668x" and it's code
\r
764 static void enterLowPower (Mcu_ModeType mcuMode )
\r
769 /* - Set the sleep bit; following a WAIT instruction, the device will go to sleep
\r
770 * - enable the 1.2V internal regulator when in sleep mode only
\r
772 * - 0x1 8k, 0x2 16k, 0x3 32k, 0x6 64k -- RAMs maintain power
\r
774 * - 0x1 32k, 0x2 64k, 0x3 128k
\r
776 WRITE32(CRP_PSCR, PSCR_SLEEP | PSCR_SLP12EN | PCSR_RAMSEL(RAMSEL_VAL));
\r
778 /* Set Recover Vector */
\r
779 #if defined(CFG_MPC5516)
\r
781 WRITE32(CRP_Z1VEC, ((uint32)&McuE_LowPowerRecoverFlash) | VLE_VAL );
\r
782 READWRITE32( CRP_RECPTR, RECPTR_FASTREC, 0 );
\r
784 Mcu_SavedHaltFlags = SIU.HLT.R;
\r
785 /* Halt everything */
\r
786 SIU.HLT.R = 0x3FFFFFFF;
\r
787 while((SIU.HLTACK.R != 0x3FFFFFFF) && (timeout<3000)) {}
\r
789 /* put Z0 in reset if not used for wakeup */
\r
790 CRP.Z0VEC.B.Z0RST = 1;
\r
792 #elif defined(CFG_MPC5668)
\r
794 WRITE32(CRP_Z6VEC, ((uint32)&McuE_LowPowerRecoverFlash) | VLE_VAL );
\r
795 READWRITE32(CRP_RECPTR,RECPTR_FASTREC,0 );
\r
797 Mcu_SavedHaltFlags[0] = SIU.HLT0.R;
\r
798 Mcu_SavedHaltFlags[1] = SIU.HLT1.R;
\r
799 /* Halt everything */
\r
800 SIU.HLT0.R = 0x037FFF3D;
\r
801 SIU.HLT1.R = 0x18000F3C;
\r
802 while((SIU.HLTACK0.R != 0x037FFF3D) && (SIU.HLTACK1.R != 0x18000F3C) && (timeout<3000)){}
\r
804 #error CPU not defined
\r
807 /* put Z0 in reset if not used for wakeup */
\r
808 CRP.Z0VEC.B.Z0RST = 1;
\r
810 /* Save context and execute wait instruction.
\r
812 * Things that matter here are
\r
813 * - Z1VEC, determines where TLB0 will point. TLB0 is written with a
\r
814 * value at startup that 4K aligned to this address.
\r
815 * - LowPower_Sleep() will save a interrupt context so we will return
\r
817 * - For devices with little RAM we don't want to impose the alignment
\r
818 * requirements there. Almost as we have to occupy a 4K block for this..
\r
819 * although the code does not take that much space.
\r
821 McuE_EnterLowPower(mcuMode);
\r
823 /* Clear sleep flags to allow pads to operate */
\r
824 CRP.PSCR.B.SLEEPF = 0x1;
\r
829 void Mcu_SetMode( Mcu_ModeType mcuMode)
\r
831 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );
\r
832 // VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );
\r
835 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
836 if( MCU_MODE_RUN == mcuMode ) {
\r
838 /* Get back to "normal" halt flags */
\r
839 #if defined(CFG_MPC5516)
\r
840 SIU.HLT.R = Mcu_SavedHaltFlags;
\r
841 #elif defined(CFG_MPC5668)
\r
842 SIU.HLT0.R = Mcu_SavedHaltFlags[0];
\r
843 SIU.HLT1.R = Mcu_SavedHaltFlags[1];
\r
846 } else if( MCU_MODE_SLEEP == mcuMode ) {
\r
848 * Follows the AN3548 from Freescale
\r
851 #if defined(USE_DMA)
\r
856 /* Set system clock to 16Mhz IRC */
\r
857 SIU.SYSCLK.B.SYSCLKSEL = 0;
\r
859 /* Put flash in low-power mode */
\r
862 /* Put QQADC in low-power mode */
\r
865 /* Set us in SLEEP mode */
\r
866 CRP.PSCR.B.SLEEP = 1;
\r
869 enterLowPower(mcuMode);
\r
872 /* NOT SUPPORTED */
\r
877 //-------------------------------------------------------------------
\r
880 * Get the system clock in Hz. It calculates the clock from the
\r
881 * different register settings in HW.
\r
883 uint32_t McuE_GetSystemClock(void)
\r
886 * System clock calculation
\r
888 * 5516 - f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));
\r
889 * 5567 - f_sys = extal * (emfd+4) / ( (eprediv+1) * ( 2^erfd ));
\r
890 * 563x - We run in legacy mode = 5567
\r
891 * 5606s - f_sys = extal * emfd / ((eprediv+1)*(2<<(erfd)));
\r
893 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
894 uint32_t eprediv = FMPLL.ESYNCR1.B.EPREDIV;
\r
895 uint32_t emfd = FMPLL.ESYNCR1.B.EMFD;
\r
896 uint32_t erfd = FMPLL.ESYNCR2.B.ERFD;
\r
897 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567) || defined(CFG_MPC5633)
\r
898 uint32_t eprediv = FMPLL.SYNCR.B.PREDIV;
\r
899 uint32_t emfd = FMPLL.SYNCR.B.MFD;
\r
900 uint32_t erfd = FMPLL.SYNCR.B.RFD;
\r
901 #elif defined(CFG_MPC560XB)
\r
902 uint32_t eprediv = CGM.FMPLL_CR.B.IDF;
\r
903 uint32_t emfd = CGM.FMPLL_CR.B.NDIV;
\r
904 uint32_t erfd = CGM.FMPLL_CR.B.ODF;
\r
905 #elif defined(CFG_MPC5606S)
\r
906 uint32_t eprediv = CGM.FMPLL[0].CR.B.IDF;
\r
907 uint32_t emfd = CGM.FMPLL[0].CR.B.NDIV;
\r
908 uint32_t erfd = CGM.FMPLL[0].CR.B.ODF;
\r
912 uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
\r
914 f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);
\r
919 #if defined(CFG_MPC5668)
\r
920 uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type) {
\r
921 uint32_t sysClock = McuE_GetSystemClock();
\r
922 vuint32_t prescaler;
\r
926 case PERIPHERAL_CLOCK_FLEXCAN_A:
\r
927 case PERIPHERAL_CLOCK_FLEXCAN_B:
\r
928 case PERIPHERAL_CLOCK_FLEXCAN_C:
\r
929 case PERIPHERAL_CLOCK_FLEXCAN_D:
\r
930 case PERIPHERAL_CLOCK_FLEXCAN_E:
\r
931 case PERIPHERAL_CLOCK_FLEXCAN_F:
\r
932 case PERIPHERAL_CLOCK_DSPI_A:
\r
933 case PERIPHERAL_CLOCK_DSPI_B:
\r
934 case PERIPHERAL_CLOCK_DSPI_C:
\r
935 case PERIPHERAL_CLOCK_DSPI_D:
\r
936 prescaler = SIU.SYSCLK.B.LPCLKDIV1;
\r
938 case PERIPHERAL_CLOCK_ESCI_A:
\r
939 case PERIPHERAL_CLOCK_ESCI_B:
\r
940 case PERIPHERAL_CLOCK_ESCI_C:
\r
941 case PERIPHERAL_CLOCK_ESCI_D:
\r
942 case PERIPHERAL_CLOCK_ESCI_E:
\r
943 case PERIPHERAL_CLOCK_ESCI_F:
\r
944 case PERIPHERAL_CLOCK_IIC_A:
\r
945 case PERIPHERAL_CLOCK_IIC_B:
\r
946 prescaler = SIU.SYSCLK.B.LPCLKDIV0;
\r
948 case PERIPHERAL_CLOCK_ADC_A:
\r
949 prescaler = SIU.SYSCLK.B.LPCLKDIV2;
\r
951 case PERIPHERAL_CLOCK_EMIOS:
\r
952 prescaler = SIU.SYSCLK.B.LPCLKDIV3;
\r
959 return sysClock/(1<<prescaler);
\r
966 * Get the peripheral clock in Hz for a specific device
\r
968 uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)
\r
970 #if defined(CFG_MPC5567)
\r
971 // No peripheral dividers on 5567.
\r
972 return McuE_GetSystemClock();
\r
974 uint32_t sysClock = McuE_GetSystemClock();
\r
975 vuint32_t prescaler;
\r
977 // See table 3.1, section 3.4.5 Peripheral Clock dividers
\r
980 case PERIPHERAL_CLOCK_FLEXCAN_A:
\r
981 case PERIPHERAL_CLOCK_DSPI_A:
\r
982 #if defined(CFG_MPC5516)
\r
983 prescaler = SIU.SYSCLK.B.LPCLKDIV0;
\r
985 #elif defined(CFG_MPC560X)
\r
986 prescaler = CGM.SC_DC[1].B.DIV;
\r
990 case PERIPHERAL_CLOCK_PIT:
\r
991 case PERIPHERAL_CLOCK_ESCI_A:
\r
992 case PERIPHERAL_CLOCK_IIC_A:
\r
993 #if defined(CFG_MPC5516)
\r
994 prescaler = SIU.SYSCLK.B.LPCLKDIV1;
\r
998 case PERIPHERAL_CLOCK_FLEXCAN_B:
\r
999 case PERIPHERAL_CLOCK_FLEXCAN_C:
\r
1000 case PERIPHERAL_CLOCK_FLEXCAN_D:
\r
1001 case PERIPHERAL_CLOCK_FLEXCAN_E:
\r
1002 case PERIPHERAL_CLOCK_FLEXCAN_F:
\r
1003 #if defined(CFG_MPC5516)
\r
1004 prescaler = SIU.SYSCLK.B.LPCLKDIV2;
\r
1006 #elif defined(CFG_MPC560X)
\r
1007 prescaler = CGM.SC_DC[1].B.DIV;
\r
1011 case PERIPHERAL_CLOCK_DSPI_B:
\r
1012 case PERIPHERAL_CLOCK_DSPI_C:
\r
1013 case PERIPHERAL_CLOCK_DSPI_D:
\r
1014 case PERIPHERAL_CLOCK_DSPI_E:
\r
1015 case PERIPHERAL_CLOCK_DSPI_F:
\r
1016 #if defined(CFG_MPC5516)
\r
1017 prescaler = SIU.SYSCLK.B.LPCLKDIV3;
\r
1021 case PERIPHERAL_CLOCK_ESCI_B:
\r
1022 case PERIPHERAL_CLOCK_ESCI_C:
\r
1023 case PERIPHERAL_CLOCK_ESCI_D:
\r
1024 case PERIPHERAL_CLOCK_ESCI_E:
\r
1025 case PERIPHERAL_CLOCK_ESCI_F:
\r
1026 case PERIPHERAL_CLOCK_ESCI_G:
\r
1027 case PERIPHERAL_CLOCK_ESCI_H:
\r
1028 #if defined(CFG_MPC5516)
\r
1029 prescaler = SIU.SYSCLK.B.LPCLKDIV4;
\r
1033 #if defined(CFG_MPC560X)
\r
1034 case PERIPHERAL_CLOCK_LIN_A:
\r
1035 case PERIPHERAL_CLOCK_LIN_B:
\r
1036 #if defined(CFG_MPC560XB)
\r
1037 case PERIPHERAL_CLOCK_LIN_C:
\r
1038 case PERIPHERAL_CLOCK_LIN_D:
\r
1040 prescaler = CGM.SC_DC[0].B.DIV;
\r
1042 case PERIPHERAL_CLOCK_EMIOS_0:
\r
1043 prescaler = CGM.SC_DC[2].B.DIV;
\r
1045 case PERIPHERAL_CLOCK_EMIOS_1:
\r
1046 prescaler = CGM.SC_DC[2].B.DIV;
\r
1049 case PERIPHERAL_CLOCK_EMIOS:
\r
1050 #if defined(CFG_MPC5516)
\r
1051 prescaler = SIU.SYSCLK.B.LPCLKDIV5;
\r
1056 case PERIPHERAL_CLOCK_MLB:
\r
1057 #if defined(CFG_MPC5516)
\r
1058 prescaler = SIU.SYSCLK.B.LPCLKDIV6;
\r
1067 return sysClock/(1<<prescaler);
\r
1073 * Function to setup the internal flash for optimal performance
\r
1076 static void Mcu_ConfigureFlash(void)
\r
1078 /* These flash settings increases the CPU performance of 7 times compared
\r
1079 to reset default settings!! */
\r
1081 #if defined(CFG_MPC5516)
\r
1082 /* Disable pipelined reads when flash options are changed. */
\r
1083 FLASH.MCR.B.PRD = 1;
\r
1085 /* Enable master prefetch for e200z1 and eDMA. */
\r
1086 FLASH.PFCRP0.B.M0PFE = 1;
\r
1087 FLASH.PFCRP0.B.M2PFE = 1;
\r
1089 /* Address pipelining control. Must be set to the same value as RWSC. */
\r
1090 FLASH.PFCRP0.B.APC = 2;
\r
1091 FLASH.PFCRP0.B.RWSC = 2;
\r
1093 /* Write wait states. */
\r
1094 FLASH.PFCRP0.B.WWSC = 1;
\r
1096 /* Enable data prefetch. */
\r
1097 FLASH.PFCRP0.B.DPFEN = 1;
\r
1099 /* Enable instruction prefetch. */
\r
1100 FLASH.PFCRP0.B.IPFEN = 1;
\r
1102 /* Prefetch algorithm. */
\r
1103 /* TODO: Ask Freescale about this option. */
\r
1104 FLASH.PFCRP0.B.PFLIM = 2;
\r
1106 /* Enable line read buffers. */
\r
1107 FLASH.PFCRP0.B.BFEN = 1;
\r
1109 /* Enable pipelined reads again. */
\r
1110 FLASH.MCR.B.PRD = 0;
\r
1111 #elif defined(CFG_MPC5668)
\r
1112 /* Check values from cookbook and MPC5668x Microcontroller Data Sheet */
\r
1114 /* Should probably trim this values */
\r
1115 const typeof(FLASH.PFCRP0.B) val = {.M0PFE = 1, .M2PFE=1, .APC=3,
\r
1116 .RWSC=3, .WWSC =1, .DPFEN =1, .IPFEN = 1, .PFLIM =2,
\r
1118 FLASH.PFCRP0.B = val;
\r
1120 /* Enable pipelined reads again. */
\r
1121 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
\r
1122 //TODO: Lägg till flash för mpc5554 &67
\r