1 /* -------------------------------- Arctic Core ------------------------------
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2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
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4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
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6 * This source code is free software; you can redistribute it and/or modify it
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7 * under the terms of the GNU General Public License version 2 as published by the
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8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
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10 * This program is distributed in the hope that it will be useful, but
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11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 * -------------------------------- Arctic Core ------------------------------*/
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17 /* ----------------------------[includes]------------------------------------*/
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20 #include "Std_Types.h"
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22 #if defined(USE_DET)
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25 #if defined(USE_DEM)
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28 #include "mpc55xx.h"
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35 #if defined(USE_DMA)
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39 //#define USE_LDEBUG_PRINTF 1
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42 /* ----------------------------[private define]------------------------------*/
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44 #define SYSCLOCK_SELECT_PLL 0x2
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46 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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48 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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49 #define CRP_BASE (0xFFFEC000ul)
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51 #error Please define CRP_BASE
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54 #define CRP_CLKSRC (CRP_BASE+0x0)
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55 #define CRP_RTCSC (CRP_BASE+0x10)
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56 #define CRP_RTCCNT (CRP_BASE+0x14)
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57 /* 40--4F differs ALOT */
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58 #define CRP_Z1VEC (CRP_BASE+0x50)
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59 #define CRP_Z6VEC (CRP_BASE+0x50)
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60 #define CRP_Z0VEC (CRP_BASE+0x54)
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61 #define CRP_RECPTR (CRP_BASE+0x58)
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62 #define CRP_PSCR (CRP_BASE+0x60)
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64 #define xVEC_xVEC(_x)
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65 #define PSCR_SLEEP 0x00008000ul
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66 #define PSCR_SLP12EN 0x00000800ul
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67 #define PCSR_RAMSEL(_x) ((_x)<<8)
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68 #define xVEC_VLE 0x00000001ul
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69 #define xVEC_xRST 0x00000002ul
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71 #define RECPTR_FASTREC 0x00000002ul
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74 #if defined(CFG_VLE)
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75 #define VLE_VAL xVEC_VLE
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80 #if defined(CFG_MPC5516 )
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81 #define RAMSEL_VAL 0x7
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82 #elif defined(CFG_MPC5668)
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83 #define RAMSEL_VAL 0x3
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85 #error Please define RAMSEL_VAL
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91 /* ----------------------------[private macro]-------------------------------*/
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94 #if defined(CFG_MPC5567)
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95 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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96 ( (_extal) * ((_emfd)+4) / (((_eprediv)+1)*(1<<(_erfd))) )
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97 #elif defined(CFG_MPC560X)
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98 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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99 ( (_extal)*(_emfd) / ((_eprediv+1)*(2<<(_erfd))) )
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101 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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102 ( (_extal) * ((_emfd)+16) / (((_eprediv)+1)*((_erfd)+1)) )
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105 /* ----------------------------[private typedef]-----------------------------*/
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108 typedef void (*vfunc_t)();
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111 /* ----------------------------[private function prototypes]-----------------*/
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112 /* ----------------------------[private variables]---------------------------*/
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114 #if defined(CFG_MPC5516)
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115 static uint32 Mcu_SavedHaltFlags;
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117 static uint32 Mcu_SavedHaltFlags[2];
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122 /* ----------------------------[private functions]---------------------------*/
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123 /* ----------------------------[public functions]----------------------------*/
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125 /* Function declarations. */
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126 static void Mcu_ConfigureFlash(void);
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129 uint32 lossOfLockCnt;
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130 uint32 lossOfClockCnt;
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134 * Type that holds all global data for Mcu
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138 // Set if Mcu_Init() have been called
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141 const Mcu_ConfigType *config;
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142 Mcu_ClockType clockSetting;
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146 /* Development error macros. */
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147 #if ( MCU_DEV_ERROR_DETECT == STD_ON )
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148 #define VALIDATE(_exp,_api,_err ) \
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150 Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
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154 #define VALIDATE_W_RV(_exp,_api,_err,_rv ) \
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156 Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
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160 #define VALIDATE(_exp,_api,_err )
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161 #define VALIDATE_W_RV(_exp,_api,_err,_rv )
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165 Mcu_GlobalType Mcu_Global =
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168 .config = &McuConfigData[0],
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171 //-------------------------------------------------------------------
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173 void Mcu_LossOfLock( void ){
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174 #if defined(USE_DEM)
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175 Dem_ReportErrorStatus(MCU_E_CLOCK_FAILURE, DEM_EVENT_STATUS_FAILED);
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180 * This interrupt may be triggered more than expected.
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181 * If you are going to use this interrupt, see [Freescale Device Errata MPC5510ACE, Rev. 10 APR 2009, errata ID: 6764].
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184 #if defined(CFG_MPC560X)
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187 Mcu_Global.stats.lossOfLockCnt++;
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189 FMPLL.SYNSR.B.LOLF = 1;
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193 //-------------------------------------------------------------------
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195 void Mcu_LossOfClock( void ){
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196 /* Should report MCU_E_CLOCK_FAILURE with DEM here */
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197 #if defined(CFG_MPC560X)
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200 Mcu_Global.stats.lossOfClockCnt++;
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202 FMPLL.SYNSR.B.LOCF = 1;
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206 #define SPR_PIR 286
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207 #define SPR_PVR 287
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209 #define CORE_PVR_E200Z1 0x81440000UL
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210 #define CORE_PVR_E200Z0 0x81710000UL
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211 #define CORE_PVR_E200Z3 0x81120000UL
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212 #define CORE_PVR_E200Z6 0x81170000UL
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213 #define CORE_PVR_E200Z65 0x81150000UL /* Is actually a 5668 */
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214 #define CORE_PVR_E200Z0H 0x817F0000UL
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226 const cpu_info_t cpu_info_list[] = {
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227 #if defined(CFG_MPC5516)
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230 .pvr = CORE_PVR_E200Z1,
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234 .pvr = CORE_PVR_E200Z0,
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236 #elif defined(CFG_MPC5567)
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239 .pvr = CORE_PVR_E200Z6,
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241 #elif defined(CFG_MPC5633)
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244 .pvr = CORE_PVR_E200Z3,
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246 #elif defined(CFG_MPC5604B)
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248 .name = "MPC5604B",
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249 .pvr = CORE_PVR_E200Z0H,
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251 #elif defined(CFG_MPC5604P)
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253 .name = "MPC5604P",
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254 .pvr = CORE_PVR_E200Z0H,
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256 #elif defined(CFG_MPC5606B)
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258 .name = "MPC5606B",
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259 .pvr = CORE_PVR_E200Z0H,
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261 #elif defined(CFG_MPC5606S)
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263 .name = "MPC5606S",
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264 .pvr = CORE_PVR_E200Z0H,
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266 #elif defined(CFG_MPC5668)
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269 .pvr = CORE_PVR_E200Z65,
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273 .pvr = CORE_PVR_E200Z0,
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278 const core_info_t core_info_list[] = {
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279 #if defined(CFG_MPC5516)
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281 .name = "CORE_E200Z1",
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282 .pvr = CORE_PVR_E200Z1,
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285 .name = "CORE_E200Z1",
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286 .pvr = CORE_PVR_E200Z1,
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288 #elif defined(CFG_MPC5567)
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290 .name = "CORE_E200Z6",
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291 .pvr = CORE_PVR_E200Z6,
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293 #elif defined(CFG_MPC5633)
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295 .name = "CORE_E200Z3",
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296 .pvr = CORE_PVR_E200Z3,
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298 #elif defined(CFG_MPC5604B)
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300 .name = "MPC5604B",
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301 .pvr = CORE_PVR_E200Z0H,
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303 #elif defined(CFG_MPC5604P)
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305 .name = "MPC5604P",
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306 .pvr = CORE_PVR_E200Z0H,
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308 #elif defined(CFG_MPC5606B)
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310 .name = "MPC5606B",
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311 .pvr = CORE_PVR_E200Z0H,
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313 #elif defined(CFG_MPC5606S)
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315 .name = "MPC5606S",
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316 .pvr = CORE_PVR_E200Z0H,
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318 #elif defined(CFG_MPC5668)
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320 .name = "CORE_E200Z65",
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321 .pvr = CORE_PVR_E200Z65,
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324 .name = "CORE_E200Z0",
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325 .pvr = CORE_PVR_E200Z1,
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331 #if !defined(ARRAY_SIZE)
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332 #define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))
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335 static const cpu_info_t *Mcu_IdentifyCpu(uint32 pvr)
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339 for (i = 0; i < ARRAY_SIZE(cpu_info_list); i++) {
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340 if (cpu_info_list[i].pvr == pvr) {
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341 return &cpu_info_list[i];
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348 static const core_info_t *Mcu_IdentifyCore(uint32 pvr)
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352 for (i = 0; i < ARRAY_SIZE(core_info_list); i++) {
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353 if (core_info_list[i].pvr == pvr) {
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354 return &core_info_list[i];
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361 static uint32 Mcu_CheckCpu( void ) {
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364 const cpu_info_t *cpuType;
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365 const core_info_t *coreType;
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367 // We have to registers to read here, PIR and PVR
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368 // pir = get_spr(SPR_PIR);
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369 pvr = get_spr(SPR_PVR);
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371 cpuType = Mcu_IdentifyCpu(pvr);
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372 coreType = Mcu_IdentifyCore(pvr);
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374 if( (cpuType == NULL) || (coreType == NULL) ) {
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379 //DEBUG(DEBUG_HIGH,"/drivers/mcu: Cpu: %s( 0x%08x )\n",cpuType->name,pvr);
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380 //DEBUG(DEBUG_HIGH,"/drivers/mcu: Core: %s( 0x%08x )\n",coreType->name,pvr);
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385 //-------------------------------------------------------------------
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387 void Mcu_Init(const Mcu_ConfigType *configPtr)
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389 VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );
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391 #if defined(CFG_MPC560X)
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392 /* Disable watchdog. Watchdog is enabled default after reset.*/
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393 SWT.SR.R = 0x0000c520; /* Write keys to clear soft lock bit */
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394 SWT.SR.R = 0x0000d928;
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395 SWT.CR.R = 0x8000010A; /* Disable watchdog */
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396 #if defined(USE_WDG)
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397 #if !defined(CFG_MPC5604P)
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398 SWT.TO.R = 0xfa00; /* set the timout to 500ms, 128khz clock */
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400 SWT.TO.R = 0x7d000; /* set the timout to 500ms, , 16khz clock */
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402 SWT.CR.R = 0x8000011B; /* enable watchdog */
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406 if( !SIMULATOR() ) {
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410 memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));
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413 Mcu_ConfigureFlash();
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415 Mcu_Global.config = configPtr;
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417 #if defined(CFG_MPC560X)
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418 /* Enable DRUN, RUN0, SAFE, RESET modes */
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419 ME.MER.R = 0x0000001D;
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420 /* MPC5604P: CMU_0 must be initialized differently from the default value
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421 in case of 8 MHz crystal. */
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422 #if defined (CFG_MPC5604P)
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423 CGM.CMU_0_CSR.R = 0x00000004;
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427 Mcu_Global.initRun = 1;
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429 if( Mcu_Global.config->McuClockSrcFailureNotification == TRUE ) {
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430 #if defined(CFG_MPC560X)
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433 ISR_INSTALL_ISR1("LossOfLock", Mcu_LossOfLock, PLL_SYNSR_LOLF, 10 , 0 );
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434 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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435 FMPLL.ESYNCR2.B.LOLIRQ = 1;
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436 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
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437 FMPLL.SYNCR.B.LOLIRQ = 1;
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439 ISR_INSTALL_ISR1("LossOfClock", Mcu_LossOfClock, PLL_SYNSR_LOLF, 10 , 0 );
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440 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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441 FMPLL.ESYNCR2.B.LOCIRQ = 1;
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442 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
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443 FMPLL.SYNCR.B.LOCIRQ = 1;
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448 #if defined(CFG_MPC5668)
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449 /* Enable ecc error reporting */
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450 ECSM.ECR.B.EPFNCR = 1;
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452 /* TODO: add support */
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456 //-------------------------------------------------------------------
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460 Mcu_Global.initRun = FALSE; // Very simple Deinit. Should we do more?
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463 //-------------------------------------------------------------------
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465 Std_ReturnType Mcu_InitRamSection(const Mcu_RamSectionType RamSection)
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467 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );
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468 VALIDATE_W_RV( ( RamSection <= Mcu_Global.config->McuRamSectors ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_PARAM_RAMSECTION, E_NOT_OK );
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470 /* NOT SUPPORTED, reason: no support for external RAM */
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475 //-------------------------------------------------------------------
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477 Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)
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479 const Mcu_ClockSettingConfigType *clockSettingsPtr;
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480 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITCLOCK_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );
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481 VALIDATE_W_RV( ( ClockSetting < Mcu_Global.config->McuClockSettings ), MCU_INITCLOCK_SERVICE_ID, MCU_E_PARAM_CLOCK, E_NOT_OK );
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483 Mcu_Global.clockSetting = ClockSetting;
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484 clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];
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486 // TODO: find out if the 5554 really works like the 5516 here
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487 // All three (16, 54, 67) used to run the same code here though, so i'm sticking it with 5516
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488 #if defined(CFG_SIMULATOR)
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490 #elif defined(CFG_MPC5516) || defined(CFG_MPC5554) || defined(CFG_MPC5668)
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492 * Fsys - System frequency ( CPU + all periperals? )
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494 * Fsys = EXTAL_FREQ *( (emfd+16) / ( (eprediv+1) * ( erfd+1 )) ) )
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497 assert((clockSettingsPtr->Pll2>=32) && (clockSettingsPtr->Pll2<=132));
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498 assert( (clockSettingsPtr->Pll1 != 6) &&
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499 (clockSettingsPtr->Pll1 != 8) &&
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500 (clockSettingsPtr->Pll1 < 10) );
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501 assert( clockSettingsPtr->Pll3 & 1); // Must be odd
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502 #elif defined(CFG_MPC5567)
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503 /* 5567 clock info:
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504 * Fsys = EXTAL_FREQ *( (emfd+4) / ( (eprediv+1) * ( 2^erfd )) ) )
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507 assert(clockSettingsPtr->Pll2 < 16);
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508 assert(clockSettingsPtr->Pll1 <= 4);
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509 assert(clockSettingsPtr->Pll3 < 8);
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512 #if defined(USE_LDEBUG_PRINTF)
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514 uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
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517 f_sys = CALC_SYSTEM_CLOCK( extal,
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518 clockSettingsPtr->Pll2,
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519 clockSettingsPtr->Pll1,
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520 clockSettingsPtr->Pll3 );
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522 //DEBUG(DEBUG_HIGH,"/drivers/mcu: F_sys will be:%08d Hz\n",f_sys);
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526 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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528 // set post divider to next valid value to ensure that an overshoot during lock phase
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529 // won't result in a too high freq
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530 FMPLL.ESYNCR2.B.ERFD = (clockSettingsPtr->Pll3 + 1) | 1;
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532 // External crystal PLL mode.
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533 FMPLL.ESYNCR1.B.CLKCFG = 7; //TODO: Hur ställa detta för 5567?
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535 // Write pll parameters.
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536 FMPLL.ESYNCR1.B.EPREDIV = clockSettingsPtr->Pll1;
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537 FMPLL.ESYNCR1.B.EMFD = clockSettingsPtr->Pll2;
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539 while(FMPLL.SYNSR.B.LOCK != 1) {};
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541 FMPLL.ESYNCR2.B.ERFD = clockSettingsPtr->Pll3;
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542 // Connect SYSCLK to FMPLL
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543 SIU.SYSCLK.B.SYSCLKSEL = SYSCLOCK_SELECT_PLL;
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544 #elif defined(CFG_MPC5604B) || defined(CFG_MPC5606B)
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545 // Write pll parameters.
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546 CGM.FMPLL_CR.B.IDF = clockSettingsPtr->Pll1;
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547 CGM.FMPLL_CR.B.NDIV = clockSettingsPtr->Pll2;
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548 CGM.FMPLL_CR.B.ODF = clockSettingsPtr->Pll3;
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550 /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */
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551 ME.RUN[0].R = 0x001F0074;
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552 /* Peri. Cfg. 1 settings: only run in RUN0 mode */
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553 ME.RUNPC[1].R = 0x00000010;
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554 /* MPC56xxB/S: select ME.RUNPC[1] */
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555 ME.PCTL[68].R = 0x01; //SIUL control
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556 ME.PCTL[91].R = 0x01; //RTC/API control
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557 ME.PCTL[92].R = 0x01; //PIT_RTI control
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558 ME.PCTL[72].R = 0x01; //eMIOS0 control
\r
559 ME.PCTL[73].R = 0x01; //eMIOS1 control
\r
560 ME.PCTL[16].R = 0x01; //FlexCAN0 control
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561 ME.PCTL[17].R = 0x01; //FlexCAN1 control
\r
562 ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */
\r
563 ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */
\r
564 ME.PCTL[32].R = 0x01; //ADC0 control
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565 #if defined(CFG_MPC5606B)
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566 ME.PCTL[33].R = 0x01; //ADC1 control
\r
568 ME.PCTL[23].R = 0x01; //DMAMUX control
\r
569 ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
570 ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
571 /* Mode Transition to enter RUN0 mode: */
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572 /* Enter RUN0 Mode & Key */
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573 ME.MCTL.R = 0x40005AF0;
\r
574 /* Enter RUN0 Mode & Inverted Key */
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575 ME.MCTL.R = 0x4000A50F;
\r
577 /* Wait for mode transition to complete */
\r
578 while (ME.GS.B.S_MTRANS) {}
\r
579 /* Verify RUN0 is the current mode */
\r
580 while(ME.GS.B.S_CURRENTMODE != 4) {}
\r
582 CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */
\r
583 CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */
\r
584 CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */
\r
586 SIU.PSMI[0].R = 0x01; /* CAN1RX on PCR43 */
\r
587 SIU.PSMI[6].R = 0x01; /* CS0/DSPI_0 on PCR15 */
\r
589 #elif defined(CFG_MPC5606S)
\r
590 // Write pll parameters.
\r
591 CGM.FMPLL[0].CR.B.IDF = clockSettingsPtr->Pll1;
\r
592 CGM.FMPLL[0].CR.B.NDIV = clockSettingsPtr->Pll2;
\r
593 CGM.FMPLL[0].CR.B.ODF = clockSettingsPtr->Pll3;
\r
595 /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */
\r
596 ME.RUN[0].R = 0x001F0074;
\r
597 /* Peri. Cfg. 1 settings: only run in RUN0 mode */
\r
598 ME.RUNPC[1].R = 0x00000010;
\r
599 /* MPC56xxB/S: select ME.RUNPC[1] */
\r
600 ME.PCTL[68].R = 0x01; //SIUL control
\r
601 ME.PCTL[91].R = 0x01; //RTC/API control
\r
602 ME.PCTL[92].R = 0x01; //PIT_RTI control
\r
603 ME.PCTL[72].R = 0x01; //eMIOS0 control
\r
604 ME.PCTL[73].R = 0x01; //eMIOS1 control
\r
605 ME.PCTL[16].R = 0x01; //FlexCAN0 control
\r
606 ME.PCTL[17].R = 0x01; //FlexCAN1 control
\r
607 ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */
\r
608 ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */
\r
609 ME.PCTL[32].R = 0x01; //ADC0 control
\r
610 ME.PCTL[23].R = 0x01; //DMAMUX control
\r
611 ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
612 ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
613 /* Mode Transition to enter RUN0 mode: */
\r
614 /* Enter RUN0 Mode & Key */
\r
615 ME.MCTL.R = 0x40005AF0;
\r
616 /* Enter RUN0 Mode & Inverted Key */
\r
617 ME.MCTL.R = 0x4000A50F;
\r
619 /* Wait for mode transition to complete */
\r
620 while (ME.GS.B.S_MTRANS) {}
\r
621 /* Verify RUN0 is the current mode */
\r
622 while(ME.GS.B.S_CURRENTMODE != 4) {}
\r
624 CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */
\r
625 CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */
\r
626 CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */
\r
628 #elif defined(CFG_MPC5604P)
\r
629 // Write pll parameters.
\r
630 CGM.FMPLL[0].CR.B.IDF = clockSettingsPtr->Pll1;
\r
631 CGM.FMPLL[0].CR.B.NDIV = clockSettingsPtr->Pll2;
\r
632 CGM.FMPLL[0].CR.B.ODF = clockSettingsPtr->Pll3;
\r
633 // PLL1 must be higher than 120MHz for PWM to work */
\r
634 CGM.FMPLL[1].CR.B.IDF = clockSettingsPtr->Pll1_1;
\r
635 CGM.FMPLL[1].CR.B.NDIV = clockSettingsPtr->Pll2_1;
\r
636 CGM.FMPLL[1].CR.B.ODF = clockSettingsPtr->Pll3_1;
\r
638 /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON, PLL1ON,syclk=PLL0 */
\r
639 ME.RUN[0].R = 0x001F00F4;
\r
640 /* Peri. Cfg. 1 settings: only run in RUN0 mode */
\r
641 ME.RUNPC[1].R = 0x00000010;
\r
643 /* MPC56xxB/S: select ME.RUNPC[1] */
\r
644 ME.PCTL[68].R = 0x01; //SIUL control
\r
645 ME.PCTL[92].R = 0x01; //PIT_RTI control
\r
646 ME.PCTL[41].R = 0x01; //flexpwm0 control
\r
647 ME.PCTL[16].R = 0x01; //FlexCAN0 control
\r
648 ME.PCTL[26].R = 0x01; //FlexCAN1(SafetyPort) control
\r
649 ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */
\r
650 ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */
\r
651 ME.PCTL[6].R = 0x01; /* MPC56xxB/P/S DSPI2 */
\r
652 ME.PCTL[7].R = 0x01; /* MPC56xxB/P/S DSPI3: */
\r
653 ME.PCTL[32].R = 0x01; //ADC0 control
\r
654 ME.PCTL[33].R = 0x01; //ADC1 control
\r
655 ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
656 ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
657 /* Mode Transition to enter RUN0 mode: */
\r
658 /* Enter RUN0 Mode & Key */
\r
659 ME.MCTL.R = 0x40005AF0;
\r
660 /* Enter RUN0 Mode & Inverted Key */
\r
661 ME.MCTL.R = 0x4000A50F;
\r
663 /* Wait for mode transition to complete */
\r
664 while (ME.GS.B.S_MTRANS) {}
\r
665 /* Verify RUN0 is the current mode */
\r
666 while(ME.GS.B.S_CURRENTMODE != 4) {}
\r
668 /* Pwm, adc, etimer clock */
\r
669 CGM.AC0SC.R = 0x05000000; /* MPC56xxP: Select FMPLL1 for aux clk 0 */
\r
670 CGM.AC0DC.R = 0x80000000; /* MPC56xxP: Enable aux clk 0 div by 1 */
\r
672 /* Safety port clock */
\r
673 CGM.AC2SC.R = 0x04000000; /* MPC56xxP: Select FMPLL0 for aux clk 2 */
\r
674 CGM.AC2DC.R = 0x80000000; /* MPC56xxP: Enable aux clk 2 div by 1 */
\r
676 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
\r
677 // Partially following the steps in MPC5567 RM..
\r
678 FMPLL.SYNCR.B.DEPTH = 0;
\r
679 FMPLL.SYNCR.B.LOLRE = 0;
\r
680 FMPLL.SYNCR.B.LOLIRQ = 0;
\r
682 FMPLL.SYNCR.B.PREDIV = clockSettingsPtr->Pll1;
\r
683 FMPLL.SYNCR.B.MFD = clockSettingsPtr->Pll2;
\r
684 FMPLL.SYNCR.B.RFD = clockSettingsPtr->Pll3;
\r
686 // Wait for PLL to sync.
\r
687 while (Mcu_GetPllStatus() != MCU_PLL_LOCKED) ;
\r
689 FMPLL.SYNCR.B.LOLIRQ = 1;
\r
695 //-------------------------------------------------------------------
\r
697 void Mcu_DistributePllClock(void)
\r
699 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );
\r
700 #if defined(CFG_MPC560XB)
\r
701 VALIDATE( ( CGM.FMPLL_CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
702 #elif defined(CFG_MPC5606S) || defined(CFG_MPC5604P)
\r
703 VALIDATE( ( CGM.FMPLL[0].CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
705 VALIDATE( ( FMPLL.SYNSR.B.LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
707 /* NOT IMPLEMENTED due to pointless function on this hardware */
\r
711 //-------------------------------------------------------------------
\r
713 Mcu_PllStatusType Mcu_GetPllStatus(void)
\r
715 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );
\r
716 Mcu_PllStatusType rv;
\r
720 #if defined(CFG_MPC560XB)
\r
721 if ( !CGM.FMPLL_CR.B.S_LOCK )
\r
723 rv = MCU_PLL_UNLOCKED;
\r
726 rv = MCU_PLL_LOCKED;
\r
728 #elif defined(CFG_MPC5606S) || defined(CFG_MPC5604P)
\r
729 if ( !CGM.FMPLL[0].CR.B.S_LOCK )
\r
731 rv = MCU_PLL_UNLOCKED;
\r
734 rv = MCU_PLL_LOCKED;
\r
737 if ( !FMPLL.SYNSR.B.LOCK )
\r
739 rv = MCU_PLL_UNLOCKED;
\r
742 rv = MCU_PLL_LOCKED;
\r
748 /* We are running on instruction set simulator. PLL is then always in sync... */
\r
749 rv = MCU_PLL_LOCKED;
\r
755 //-------------------------------------------------------------------
\r
757 Mcu_ResetType Mcu_GetResetReason(void)
\r
761 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );
\r
763 #if defined(CFG_MPC560X)
\r
764 if( RGM.FES.B.F_SOFT ) {
\r
766 } else if( RGM.DES.B.F_SWT ) {
\r
767 rv = MCU_WATCHDOG_RESET;
\r
768 } else if( RGM.DES.B.F_POR ) {
\r
769 rv = MCU_POWER_ON_RESET;
\r
771 rv = MCU_RESET_UNDEFINED;
\r
774 if( SIU.RSR.B.SSRS ) {
\r
776 } else if( SIU.RSR.B.WDRS ) {
\r
777 rv = MCU_WATCHDOG_RESET;
\r
778 } else if( SIU.RSR.B.PORS || SIU.RSR.B.ERS ) {
\r
779 rv = MCU_POWER_ON_RESET;
\r
781 rv = MCU_RESET_UNDEFINED;
\r
788 //-------------------------------------------------------------------
\r
790 Mcu_RawResetType Mcu_GetResetRawValue(void)
\r
792 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_GETRESETRAWVALUE_UNINIT_RV );
\r
794 if( !Mcu_Global.initRun ) {
\r
795 return MCU_GETRESETRAWVALUE_UNINIT_RV;
\r
798 #if defined(CFG_MPC560X)
\r
809 //-------------------------------------------------------------------
\r
811 #if ( MCU_PERFORM_RESET_API == STD_ON )
\r
812 void Mcu_PerformReset(void)
\r
814 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_PERFORMRESET_SERVICE_ID, MCU_E_UNINIT );
\r
817 #if defined(CFG_MPC560X)
\r
818 ME.MCTL.R = 0x00005AF0;
\r
819 ME.MCTL.R = 0x0000A50F;
\r
821 while (ME.GS.B.S_MTRANS) {}
\r
822 while(ME.GS.B.S_CURRENTMODE != 0) {}
\r
824 SIU.SRCR.B.SSR = 1;
\r
830 //-------------------------------------------------------------------
\r
832 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
836 * Application Notes!
\r
837 * - AN3584, "MPC5510 Family Low Power Features"
\r
838 * Since it's not complete also check MPC5668
\r
839 * - AN4150 , "Using Sleep Mode on the MPC5668x" and it's code
\r
844 static void enterLowPower (Mcu_ModeType mcuMode )
\r
848 uint32 timeout = 0;
\r
849 /* - Set the sleep bit; following a WAIT instruction, the device will go to sleep
\r
850 * - enable the 1.2V internal regulator when in sleep mode only
\r
852 * - 0x1 8k, 0x2 16k, 0x3 32k, 0x6 64k -- RAMs maintain power
\r
854 * - 0x1 32k, 0x2 64k, 0x3 128k
\r
857 /* Set Recover Vector */
\r
858 #if defined(CFG_MPC5516)
\r
859 WRITE32(CRP_PSCR, PSCR_SLEEP | PSCR_SLP12EN | PCSR_RAMSEL(RAMSEL_VAL));
\r
861 WRITE32(CRP_Z1VEC, ((uint32)&McuE_LowPowerRecoverFlash) | VLE_VAL );
\r
862 READWRITE32( CRP_RECPTR, RECPTR_FASTREC, 0 );
\r
864 Mcu_SavedHaltFlags = SIU.HLT.R;
\r
865 /* Halt everything */
\r
866 SIU.HLT.R = 0x3FFFFFFF;
\r
867 while((SIU.HLTACK.R != 0x3FFFFFFF) && (timeout++<3000)) {}
\r
869 /* put Z0 in reset if not used for wakeup */
\r
870 CRP.Z0VEC.B.Z0RST = 1;
\r
872 #elif defined(CFG_MPC5668)
\r
873 READWRITE32(CRP_PSCR, (PSCR_SLEEP | PSCR_SLP12EN | PCSR_RAMSEL(0x7)), (PSCR_SLEEP | PSCR_SLP12EN | PCSR_RAMSEL(RAMSEL_VAL)));
\r
874 WRITE32(CRP_Z6VEC, ((uint32)&McuE_LowPowerRecoverFlash) | VLE_VAL );
\r
875 READWRITE32(CRP_RECPTR,RECPTR_FASTREC,0 );
\r
877 Mcu_SavedHaltFlags[0] = SIU.HLT0.R;
\r
878 Mcu_SavedHaltFlags[1] = SIU.HLT1.R;
\r
879 /* Halt everything */
\r
880 SIU.HLT0.R = 0x037FFF3D;
\r
881 SIU.HLT1.R = 0x18000F3C;
\r
882 while((SIU.HLTACK0.R != 0x037FFF3D) && (SIU.HLTACK1.R != 0x18000F3C) && (timeout<3000)){}
\r
884 #error CPU not defined
\r
887 /* put Z0 in reset if not used for wakeup */
\r
888 CRP.Z0VEC.B.Z0RST = 1;
\r
890 /* Save context and execute wait instruction.
\r
892 * Things that matter here are
\r
893 * - Z1VEC, determines where TLB0 will point. TLB0 is written with a
\r
894 * value at startup that 4K aligned to this address.
\r
895 * - LowPower_Sleep() will save a interrupt context so we will return
\r
897 * - For devices with little RAM we don't want to impose the alignment
\r
898 * requirements there. Almost as we have to occupy a 4K block for this..
\r
899 * although the code does not take that much space.
\r
901 McuE_EnterLowPower(mcuMode);
\r
903 /* Clear sleep flags to allow pads to operate */
\r
904 CRP.PSCR.B.SLEEPF = 0x1;
\r
909 void Mcu_SetMode( Mcu_ModeType mcuMode)
\r
911 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );
\r
912 // VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );
\r
915 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
916 if( MCU_MODE_RUN == mcuMode ) {
\r
918 /* Get back to "normal" halt flags */
\r
919 #if defined(CFG_MPC5516)
\r
920 SIU.HLT.R = Mcu_SavedHaltFlags;
\r
921 #elif defined(CFG_MPC5668)
\r
922 SIU.HLT0.R = Mcu_SavedHaltFlags[0];
\r
923 SIU.HLT1.R = Mcu_SavedHaltFlags[1];
\r
926 } else if( MCU_MODE_SLEEP == mcuMode ) {
\r
928 * Follows the AN3548 from Freescale
\r
931 #if defined(USE_DMA)
\r
936 /* Set system clock to 16Mhz IRC */
\r
937 SIU.SYSCLK.B.SYSCLKSEL = 0;
\r
939 /* Put flash in low-power mode */
\r
942 /* Put QQADC in low-power mode */
\r
945 /* Set us in SLEEP mode */
\r
946 CRP.PSCR.B.SLEEP = 1;
\r
949 enterLowPower(mcuMode);
\r
952 /* NOT SUPPORTED */
\r
957 //-------------------------------------------------------------------
\r
960 * Get the system clock in Hz. It calculates the clock from the
\r
961 * different register settings in HW.
\r
963 uint32_t McuE_GetSystemClock(void)
\r
966 * System clock calculation
\r
968 * 5516 - f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));
\r
969 * 5567 - f_sys = extal * (emfd+4) / ( (eprediv+1) * ( 2^erfd ));
\r
970 * 563x - We run in legacy mode = 5567
\r
971 * 5606s - f_sys = extal * emfd / ((eprediv+1)*(2<<(erfd)));
\r
973 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
974 uint32_t eprediv = FMPLL.ESYNCR1.B.EPREDIV;
\r
975 uint32_t emfd = FMPLL.ESYNCR1.B.EMFD;
\r
976 uint32_t erfd = FMPLL.ESYNCR2.B.ERFD;
\r
977 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567) || defined(CFG_MPC5633)
\r
978 uint32_t eprediv = FMPLL.SYNCR.B.PREDIV;
\r
979 uint32_t emfd = FMPLL.SYNCR.B.MFD;
\r
980 uint32_t erfd = FMPLL.SYNCR.B.RFD;
\r
981 #elif defined(CFG_MPC560XB)
\r
982 uint32_t eprediv = CGM.FMPLL_CR.B.IDF;
\r
983 uint32_t emfd = CGM.FMPLL_CR.B.NDIV;
\r
984 uint32_t erfd = CGM.FMPLL_CR.B.ODF;
\r
985 #elif defined(CFG_MPC5606S) || defined(CFG_MPC5604P)
\r
986 uint32_t eprediv = CGM.FMPLL[0].CR.B.IDF;
\r
987 uint32_t emfd = CGM.FMPLL[0].CR.B.NDIV;
\r
988 uint32_t erfd = CGM.FMPLL[0].CR.B.ODF;
\r
992 uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
\r
994 f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);
\r
999 #if defined(CFG_MPC5668)
\r
1000 uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type) {
\r
1001 uint32_t sysClock = McuE_GetSystemClock();
\r
1002 vuint32_t prescaler;
\r
1006 case PERIPHERAL_CLOCK_FLEXCAN_A:
\r
1007 case PERIPHERAL_CLOCK_FLEXCAN_B:
\r
1008 case PERIPHERAL_CLOCK_FLEXCAN_C:
\r
1009 case PERIPHERAL_CLOCK_FLEXCAN_D:
\r
1010 case PERIPHERAL_CLOCK_FLEXCAN_E:
\r
1011 case PERIPHERAL_CLOCK_FLEXCAN_F:
\r
1012 case PERIPHERAL_CLOCK_DSPI_A:
\r
1013 case PERIPHERAL_CLOCK_DSPI_B:
\r
1014 case PERIPHERAL_CLOCK_DSPI_C:
\r
1015 case PERIPHERAL_CLOCK_DSPI_D:
\r
1016 prescaler = SIU.SYSCLK.B.LPCLKDIV1;
\r
1018 case PERIPHERAL_CLOCK_ESCI_A:
\r
1019 case PERIPHERAL_CLOCK_ESCI_B:
\r
1020 case PERIPHERAL_CLOCK_ESCI_C:
\r
1021 case PERIPHERAL_CLOCK_ESCI_D:
\r
1022 case PERIPHERAL_CLOCK_ESCI_E:
\r
1023 case PERIPHERAL_CLOCK_ESCI_F:
\r
1024 case PERIPHERAL_CLOCK_IIC_A:
\r
1025 case PERIPHERAL_CLOCK_IIC_B:
\r
1026 prescaler = SIU.SYSCLK.B.LPCLKDIV0;
\r
1028 case PERIPHERAL_CLOCK_ADC_A:
\r
1029 prescaler = SIU.SYSCLK.B.LPCLKDIV2;
\r
1031 case PERIPHERAL_CLOCK_EMIOS:
\r
1032 prescaler = SIU.SYSCLK.B.LPCLKDIV3;
\r
1039 return sysClock/(1<<prescaler);
\r
1043 #elif defined (CFG_MPC5604P)
\r
1046 * Get the peripheral clock in Hz for a specific device
\r
1048 uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)
\r
1050 uint32_t sysClock = McuE_GetSystemClock();
\r
1051 vuint32_t prescaler;
\r
1053 // See table 3.1, section 3.4.5 Peripheral Clock dividers
\r
1056 //case PERIPHERAL_CLOCK_ADC_0:
\r
1057 //case PERIPHERAL_CLOCK_ADC_1:
\r
1058 //case PERIPHERAL_CLOCK_ETIMER_0:
\r
1059 //case PERIPHERAL_CLOCK_ETIMER_1:
\r
1060 case PERIPHERAL_CLOCK_FLEXPWM_0:
\r
1062 uint32_t eprediv = CGM.FMPLL[1].CR.B.IDF;
\r
1063 uint32_t emfd = CGM.FMPLL[1].CR.B.NDIV;
\r
1064 uint32_t erfd = CGM.FMPLL[1].CR.B.ODF;
\r
1067 uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
\r
1068 f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);
\r
1070 prescaler = CGM.AC0DC.B.DIV0;
\r
1071 return f_sys/(1<<prescaler);
\r
1074 case PERIPHERAL_CLOCK_FLEXCAN_A:
\r
1075 case PERIPHERAL_CLOCK_FLEXCAN_B:
\r
1076 case PERIPHERAL_CLOCK_FLEXCAN_C:
\r
1077 case PERIPHERAL_CLOCK_FLEXCAN_D:
\r
1078 case PERIPHERAL_CLOCK_FLEXCAN_E:
\r
1079 case PERIPHERAL_CLOCK_FLEXCAN_F:
\r
1080 case PERIPHERAL_CLOCK_DSPI_A:
\r
1081 case PERIPHERAL_CLOCK_DSPI_B:
\r
1082 case PERIPHERAL_CLOCK_DSPI_C:
\r
1083 case PERIPHERAL_CLOCK_DSPI_D:
\r
1084 case PERIPHERAL_CLOCK_DSPI_E:
\r
1085 case PERIPHERAL_CLOCK_DSPI_F:
\r
1086 case PERIPHERAL_CLOCK_PIT:
\r
1087 case PERIPHERAL_CLOCK_LIN_A:
\r
1088 case PERIPHERAL_CLOCK_LIN_B:
\r
1089 case PERIPHERAL_CLOCK_LIN_C:
\r
1090 case PERIPHERAL_CLOCK_LIN_D:
\r
1099 return sysClock/(1<<prescaler);
\r
1104 * Get the peripheral clock in Hz for a specific device
\r
1106 uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)
\r
1108 #if defined(CFG_MPC5567)
\r
1109 // No peripheral dividers on 5567.
\r
1110 return McuE_GetSystemClock();
\r
1112 uint32_t sysClock = McuE_GetSystemClock();
\r
1113 vuint32_t prescaler;
\r
1115 // See table 3.1, section 3.4.5 Peripheral Clock dividers
\r
1118 case PERIPHERAL_CLOCK_FLEXCAN_A:
\r
1119 case PERIPHERAL_CLOCK_DSPI_A:
\r
1120 #if defined(CFG_MPC5516)
\r
1121 prescaler = SIU.SYSCLK.B.LPCLKDIV0;
\r
1123 #elif defined(CFG_MPC560X)
\r
1124 prescaler = CGM.SC_DC[1].B.DIV;
\r
1128 case PERIPHERAL_CLOCK_PIT:
\r
1129 case PERIPHERAL_CLOCK_ESCI_A:
\r
1130 case PERIPHERAL_CLOCK_IIC_A:
\r
1131 #if defined(CFG_MPC5516)
\r
1132 prescaler = SIU.SYSCLK.B.LPCLKDIV1;
\r
1136 case PERIPHERAL_CLOCK_FLEXCAN_B:
\r
1137 case PERIPHERAL_CLOCK_FLEXCAN_C:
\r
1138 case PERIPHERAL_CLOCK_FLEXCAN_D:
\r
1139 case PERIPHERAL_CLOCK_FLEXCAN_E:
\r
1140 case PERIPHERAL_CLOCK_FLEXCAN_F:
\r
1141 #if defined(CFG_MPC5516)
\r
1142 prescaler = SIU.SYSCLK.B.LPCLKDIV2;
\r
1144 #elif defined(CFG_MPC560X)
\r
1145 prescaler = CGM.SC_DC[1].B.DIV;
\r
1149 case PERIPHERAL_CLOCK_DSPI_B:
\r
1150 case PERIPHERAL_CLOCK_DSPI_C:
\r
1151 case PERIPHERAL_CLOCK_DSPI_D:
\r
1152 case PERIPHERAL_CLOCK_DSPI_E:
\r
1153 case PERIPHERAL_CLOCK_DSPI_F:
\r
1154 #if defined(CFG_MPC5516)
\r
1155 prescaler = SIU.SYSCLK.B.LPCLKDIV3;
\r
1159 case PERIPHERAL_CLOCK_ESCI_B:
\r
1160 case PERIPHERAL_CLOCK_ESCI_C:
\r
1161 case PERIPHERAL_CLOCK_ESCI_D:
\r
1162 case PERIPHERAL_CLOCK_ESCI_E:
\r
1163 case PERIPHERAL_CLOCK_ESCI_F:
\r
1164 case PERIPHERAL_CLOCK_ESCI_G:
\r
1165 case PERIPHERAL_CLOCK_ESCI_H:
\r
1166 #if defined(CFG_MPC5516)
\r
1167 prescaler = SIU.SYSCLK.B.LPCLKDIV4;
\r
1171 #if defined(CFG_MPC560X)
\r
1172 case PERIPHERAL_CLOCK_LIN_A:
\r
1173 case PERIPHERAL_CLOCK_LIN_B:
\r
1174 #if defined(CFG_MPC560XB) || defined(CFG_MPC5604P)
\r
1175 case PERIPHERAL_CLOCK_LIN_C:
\r
1176 case PERIPHERAL_CLOCK_LIN_D:
\r
1178 prescaler = CGM.SC_DC[0].B.DIV;
\r
1180 case PERIPHERAL_CLOCK_EMIOS_0:
\r
1181 prescaler = CGM.SC_DC[2].B.DIV;
\r
1183 case PERIPHERAL_CLOCK_EMIOS_1:
\r
1184 prescaler = CGM.SC_DC[2].B.DIV;
\r
1187 case PERIPHERAL_CLOCK_EMIOS:
\r
1188 #if defined(CFG_MPC5516)
\r
1189 prescaler = SIU.SYSCLK.B.LPCLKDIV5;
\r
1194 case PERIPHERAL_CLOCK_MLB:
\r
1195 #if defined(CFG_MPC5516)
\r
1196 prescaler = SIU.SYSCLK.B.LPCLKDIV6;
\r
1205 return sysClock/(1<<prescaler);
\r
1211 * Get frequency of the oscillator
\r
1213 uint32_t McuE_GetClockReferencePointFrequency(void)
\r
1215 return Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
\r
1219 * Function to setup the internal flash for optimal performance
\r
1222 static void Mcu_ConfigureFlash(void)
\r
1224 /* These flash settings increases the CPU performance of 7 times compared
\r
1225 to reset default settings!! */
\r
1227 #if defined(CFG_MPC5516)
\r
1228 /* Disable pipelined reads when flash options are changed. */
\r
1229 FLASH.MCR.B.PRD = 1;
\r
1231 /* Enable master prefetch for e200z1 and eDMA. */
\r
1232 FLASH.PFCRP0.B.M0PFE = 1;
\r
1233 FLASH.PFCRP0.B.M2PFE = 1;
\r
1235 /* Address pipelining control. Must be set to the same value as RWSC. */
\r
1236 FLASH.PFCRP0.B.APC = 2;
\r
1237 FLASH.PFCRP0.B.RWSC = 2;
\r
1239 /* Write wait states. */
\r
1240 FLASH.PFCRP0.B.WWSC = 1;
\r
1242 /* Enable data prefetch. */
\r
1243 FLASH.PFCRP0.B.DPFEN = 1;
\r
1245 /* Enable instruction prefetch. */
\r
1246 FLASH.PFCRP0.B.IPFEN = 1;
\r
1248 /* Prefetch algorithm. */
\r
1249 /* TODO: Ask Freescale about this option. */
\r
1250 FLASH.PFCRP0.B.PFLIM = 2;
\r
1252 /* Enable line read buffers. */
\r
1253 FLASH.PFCRP0.B.BFEN = 1;
\r
1255 /* Enable pipelined reads again. */
\r
1256 FLASH.MCR.B.PRD = 0;
\r
1257 #elif defined(CFG_MPC5668)
\r
1258 /* Check values from cookbook and MPC5668x Microcontroller Data Sheet */
\r
1260 /* Should probably trim this values */
\r
1261 const typeof(FLASH.PFCRP0.B) val = {.M0PFE = 1, .M2PFE=1, .APC=3,
\r
1262 .RWSC=3, .WWSC =1, .DPFEN =1, .IPFEN = 1, .PFLIM =2,
\r
1264 FLASH.PFCRP0.B = val;
\r
1266 /* Enable pipelined reads again. */
\r
1267 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
\r
1268 //TODO: Lägg till flash för mpc5554 &67
\r
1272 uint32 EccErrReg = 0;
\r
1274 void McuE_GetECCError( uint32 *err ) {
\r
1276 /* Clear interrupt flag */
\r
1277 #if defined(CFG_MPC5668)
\r
1278 if(ECSM.ESR.B.PFNCE){
\r
1279 ECSM.ESR.B.PFNCE = 1;
\r
1286 /* Clear stored */
\r