AssociationExample HPLCC2420
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Mica
HPLCC2420C
configuration HPLCC2420C {
provides {
interface StdControl;
interface HPLCC2420;
interface HPLCC2420FIFO;
interface HPLCC2420RAM;
}
}
implementation
{
components HPLCC2420M, HPLCC2420FIFOM;
//
StdControl = HPLCC2420M;
HPLCC2420 = HPLCC2420M;
HPLCC2420FIFO = HPLCC2420FIFOM;
HPLCC2420RAM = HPLCC2420M;
}
HPLCC2420M
module HPLCC2420M {
provides {
interface StdControl;
interface HPLCC2420;
interface HPLCC2420RAM;
}
}
implementation
{
norace bool bSpiAvail; //true if Spi bus available
norace uint8_t* rambuf;
norace uint8_t ramlen;
norace uint16_t ramaddr;
//
/*********************************************************
* function: init
* set Atmega pin directions for cc2420
* enable SPI master bus
********************************************************/
command result_t StdControl.init() {
//
bSpiAvail = TRUE;
TOSH_MAKE_MISO_INPUT();
TOSH_MAKE_MOSI_OUTPUT();
TOSH_MAKE_SPI_SCK_OUTPUT();
TOSH_MAKE_CC_RSTN_OUTPUT();
TOSH_MAKE_CC_VREN_OUTPUT();
TOSH_MAKE_CC_CS_OUTPUT();
TOSH_MAKE_CC_FIFOP1_INPUT();
TOSH_MAKE_CC_CCA_INPUT();
TOSH_MAKE_CC_SFD_INPUT();
TOSH_MAKE_CC_FIFO_INPUT();
atomic {
TOSH_MAKE_SPI_SCK_OUTPUT();
TOSH_MAKE_MISO_INPUT(); // miso
TOSH_MAKE_MOSI_OUTPUT(); // mosi
sbi(SPSR, SPI2X); // Double speed spi clock
sbi(SPCR, MSTR); // Set master mode
cbi(SPCR, CPOL); // Set proper polarity...
cbi(SPCR, CPHA); // ...and phase
cbi(SPCR, SPR1); // set clock, fosc/2 (~3.6 Mhz)
cbi(SPCR, SPR0);
// sbi(SPCR, SPIE); // enable spi port interrupt
sbi(SPCR, SPE); // enable spie port
}
return SUCCESS;
}
//
command result_t StdControl.start() { return SUCCESS; }
command result_t StdControl.stop() { return SUCCESS; }
//
/*********************************************************
* function: enableFIFOP
* enable CC2420 fifop interrupt
CC2420 is configured for FIFOP interrupt on RXFIFO > Thresh
where thresh is programmed in CC2420Const.h CP_IOCFGO reg.
Threshold is 127 asof 15apr04 (AlmostFull)
FIFOP is asserted as long as RXFIFO>Threshold
FIFOP is active LOW
********************************************************/
async command result_t HPLCC2420.enableFIFOP(){
cbi(EICRB,ISC60); //trigger on low level
// cbi(EICRB,ISC61); //low level
sbi(EICRB,ISC61); //falling edge for standard release
CC2420_FIFOP_INT_ENABLE();
return SUCCESS;
}
/*********************************************************
* function: disbleFIFOP
* disable CC2420 fifop interrupt
********************************************************/
async command result_t HPLCC2420.disableFIFOP(){
CC2420_FIFOP_INT_DISABLE();
return SUCCESS;
}
//
TOSH_SIGNAL(TOSH_CC_FIFOP_INT) {
// signal the interrupt
signal HPLCC2420.FIFOPIntr();
}
/*
* .............
*
*/
}//HPLCC2420M.nc
Telos
HPLCC2420C
configuration HPLCC2420C {
provides {
interface StdControl;
interface HPLCC2420;
interface HPLCC2420RAM;
interface HPLCC2420FIFO;
//interface HPLCC2420Interrupt as InterruptFIFOP;
}
}
implementation
{
components HPLCC2420M
, HPLUSART0M
// , HPLCC2420InterruptM
, MSP430InterruptC
, BusArbitrationC;
//
StdControl = BusArbitrationC;
StdControl = HPLCC2420M;
HPLCC2420 = HPLCC2420M;
HPLCC2420RAM = HPLCC2420M;
HPLCC2420FIFO = HPLCC2420M;
//
//InterruptFIFOP = HPLCC2420InterruptM.FIFOP;
//InterruptFIFO = HPLCC2420InterruptM.FIFO;
//
HPLCC2420M.USARTControl -> HPLUSART0M;
HPLCC2420M.BusArbitration -> BusArbitrationC.BusArbitration[unique("BusArbitration")];
//
HPLCC2420M.FIFOPInterrupt -> MSP430InterruptC.Port10;
//HPLCC2420InterruptM.FIFOInterrupt -> MSP430InterruptC.Port13;
}
HPLCC2420M
module HPLCC2420M {
provides {
interface StdControl;
interface HPLCC2420;
interface HPLCC2420RAM;
interface HPLCC2420FIFO;
}
uses {
interface HPLUSARTControl as USARTControl;
interface BusArbitration;
interface MSP430Interrupt as FIFOPInterrupt;
}
}
implementation
{
//
norace uint8_t* txbuf;
norace uint8_t* rxbuf;
norace uint8_t* rambuf;
norace uint8_t* rxrambuf;
norace uint8_t txlen;
norace uint8_t rxlen;
norace uint8_t ramlen;
norace uint16_t ramaddr;
norace uint8_t rxramlen;
norace uint16_t rxramaddr;
norace struct {
bool enabled : 1;
bool busy : 1;
bool rxbufBusy : 1;
bool txbufBusy : 1;
} f; // f for flags
/**
* Zero out the reserved bits since they can be either 0 or 1.
* This allows the use of "if !cmd(x)" in the radio stack
*/
uint8_t adjustStatusByte(uint8_t status) {
return status & 0x7E;
}
//
command result_t StdControl.init() {
atomic {
f.busy = f.enabled = f.rxbufBusy = f.txbufBusy = FALSE;
}
TOSH_SET_RADIO_CSN_PIN();
TOSH_MAKE_RADIO_CSN_OUTPUT();
call USARTControl.setModeSPI();
call USARTControl.disableRxIntr();
call USARTControl.disableTxIntr();
return SUCCESS;
}
command result_t StdControl.start() {
atomic {
if (!f.busy) {
TOSH_SET_RADIO_CSN_PIN();
TOSH_MAKE_RADIO_CSN_OUTPUT();
call USARTControl.setModeSPI();
call USARTControl.disableRxIntr();
call USARTControl.disableTxIntr();
f.busy = f.rxbufBusy = f.txbufBusy = FALSE;
f.enabled = TRUE;
}
}
return SUCCESS;
}
command result_t StdControl.stop() {
atomic {
// if we're not in the middle of doing something, we can shut off the
// SPI operations too
if (!f.busy)
call USARTControl.disableSPI();
f.enabled = FALSE;
}
return SUCCESS;
}
/*********************************************************
* function: enableFIFOP
* enable CC2420 fifop interrupt
CC2420 is configured for FIFOP interrupt on RXFIFO > Thresh
where thresh is programmed in CC2420Const.h CP_IOCFGO reg.
Threshold is 127 asof 15apr04 (AlmostFull)
FIFOP is asserted as long as RXFIFO>Threshold
FIFOP is active LOW!!!!!!!!!!
********************************************************/
async command result_t HPLCC2420.enableFIFOP(){
atomic {
call FIFOPInterrupt.disable();
call FIFOPInterrupt.clear();
//call FIFOPInterrupt.edge(low_to_high); <- problem
call FIFOPInterrupt.enable();
}
return SUCCESS;
}
/*********************************************************
* function: disbleFIFOP
* disable CC2420 fifop interrupt
********************************************************/
async command result_t HPLCC2420.disableFIFOP(){
atomic {
call FIFOPInterrupt.disable();
call FIFOPInterrupt.clear();
}
return SUCCESS;
}
/**
* Event fired by lower level interrupt dispatch for FIFOP
*/
async event void FIFOPInterrupt.fired(){
//result_t val = SUCCESS;
call FIFOPInterrupt.clear();
// val = signal FIFOP.fired(); <- problem
// if (val == FAIL) {
call FIFOPInterrupt.disable();
call FIFOPInterrupt.clear();
// }
}
/*
* default async event result_t FIFOP.fired() { return FAIL; } <- problem
*/
/*********************************************************
/*
* ........................
*/
} //HPLCC2420M
HPLCC2420InterruptM
module HPLCC2420InterruptM {
provides {
interface HPLCC2420Interrupt as FIFOP;
interface HPLCC2420Interrupt as FIFO;
interface HPLCC2420Interrupt as CCA;
interface HPLCC2420Capture as SFD;
}
uses {
interface MSP430Interrupt as FIFOPInterrupt;
interface MSP430Interrupt as FIFOInterrupt;
interface MSP430Interrupt as CCAInterrupt;
interface MSP430Capture as SFDCapture;
interface MSP430TimerControl as SFDControl;
}
}
implementation
{
// ************* FIFOP Interrupt handlers and dispatch *************
/**
* enable an edge interrupt on the FIFOP pin
*/
async command result_t FIFOP.startWait(bool low_to_high) {
atomic {
call FIFOPInterrupt.disable();
call FIFOPInterrupt.clear();
call FIFOPInterrupt.edge(low_to_high);
call FIFOPInterrupt.enable();
}
return SUCCESS;
}
/**
* disables FIFOP interrupts
*/
async command result_t FIFOP.disable() {
atomic {
call FIFOPInterrupt.disable();
call FIFOPInterrupt.clear();
}
return SUCCESS;
}
/**
* Event fired by lower level interrupt dispatch for FIFOP
*/
async event void FIFOPInterrupt.fired() {
result_t val = SUCCESS;
call FIFOPInterrupt.clear();
val = signal FIFOP.fired();
if (val == FAIL) {
call FIFOPInterrupt.disable();
call FIFOPInterrupt.clear();
}
}
default async event result_t FIFOP.fired() { return FAIL; }
/*
* ..........................
*/
} // HPLCC2420InterruptM