Xilinx: ARM: DMA: Updated to latest kernel changes.
In the latest kernel, there are some API changes and also
there is a new enum defined. This patch is created to
update these changes. The changes are in brief,
1. API 'prep_slave_sg' is modified to take an additional
argument 'void *context'.
2. A new enum 'dma_transfer_direction' has been added.
This replaces 'dma_data_direction' enum.
All the files which need this changes are updated.
Xilinx: ARM: DMA: Support for External Frame Sync feature.
There is a new feature in VDMA IP v5.02a, which needs
support from the driver. This patch has been created
to configure this external frame sync feature.
John Linn [Wed, 19 Sep 2012 20:55:57 +0000 (13:55 -0700)]
Xilinx: ARM: MTD: m25p80: fix dual qspi bug in flash
The last change that was done to make the dual QSPI
work from device tree only without a kernel config
change had a bug which was preventing the 2nd 16 MB
of flash from working on the ZC706.
If no OPPs exist, creating the freq_table fails. Error
handling in this case worked for the first core to
execute the cpufreq init routine. But a following core
would have unconditionally called
cpufreq_frequency_table_cpuinfo() causing a NULL pointer
dereference.
Soren Brinkmann [Thu, 30 Aug 2012 11:24:52 +0000 (04:24 -0700)]
Xilinx: ARM: xi2cps: Error handling
Using clk_prepare_enable() and clk_disable_unprepare() in favor of
calling (un)prepare and dis/enable routines individually.
Honoring clk_prepare_enable() return code to recognize an error.
Soren Brinkmann [Thu, 30 Aug 2012 10:02:55 +0000 (03:02 -0700)]
Xilinx: ARM: xemacps: Error handling
Using clk_prepare_enable() and clk_disable_unprepare() in favor of
calling (un)prepare and dis/enable routines individually.
Honoring clk_prepare_enable() return code to recognize an error.
Xilinx: ARM: xemacps: Enable clocks before accessing HW
This patch fixes an issue where hardware registers may be
accessed before the device clocks are enabled.
Also, error handling is improved in the questionable code
section.
Soren Brinkmann [Thu, 30 Aug 2012 08:53:30 +0000 (01:53 -0700)]
Xilinx: ARM: xuartps: Error handling
Using clk_prepare_enable() and clk_disable_unprepare() in favor of
calling (un)prepare and dis/enable routines individually.
Honoring clk_prepare_enable() return code to recognize an error.
Soren Brinkmann [Thu, 30 Aug 2012 07:51:38 +0000 (00:51 -0700)]
Xilinx: ARM: xgpiops: Error handling
Using clk_prepare_enable() and clk_disable_unprepare() in favor of
calling (un)prepare and dis/enable routines individually.
Honoring clk_prepare_enable() return code to recognize an error.
Soren Brinkmann [Wed, 29 Aug 2012 14:03:35 +0000 (07:03 -0700)]
Xilinx: ARM: timer: Correct error handling
With this patch timer init falls back
to device tree information if the timer clock is not found through
the clock framework. The DT path in turn falls back to hard
coded defaults if no matching node and property is found.
The behavior in case the clock lookup fails is the same as the
pre-common_clk behavior.
Soren Brinkmann [Wed, 29 Aug 2012 13:45:02 +0000 (06:45 -0700)]
Xilinx: ARM: timer: Remove useless conditionals
When porting the timer to use the common clock framework
it was assumed it is possible to compile a Zynq kernel
w/ or w/o COMMON_CLK defined and conditional compilation had
been added accordingly.
Turns out this assumption was wrong and building for Zynq always
defines COMMON_CLK rendering the associated conditionals useless.
This patch provides a PS_CLK frequency through the DT
for the ep107 platform. The provided frequency is far too
high and may brake a lot of subsystems. But on the other hand,
it results in a working UART, which enables to boot into a
somewhat usable system.
Soren Brinkmann [Wed, 13 Jun 2012 12:01:44 +0000 (05:01 -0700)]
Xilinx: ARM: Copying gic.c from mainline.
gic_set_cpu caused compilation warnings regarding type mismatches between a
raw_spin_lock used with spin_lock functions.
The function does not seem to be called from anywhere and is not present in
mainline.
This patch simply overwrites arch/arm/common/gic.c with the version from
mainline.
Suneel [Thu, 30 Aug 2012 11:57:05 +0000 (17:27 +0530)]
Xilinx: ARM: I2C: Support for TI PMBus Controllers on ZC702
This patch adds support for I2C_M_RECV_LEN flag and
SMBUS Block Read call in I2C Controller driver.
This support is required by TI PMBus controller driver.
Soren Brinkmann [Fri, 24 Aug 2012 09:07:04 +0000 (02:07 -0700)]
Xilinx: ARM: clk: Remove unsupported leaf clocks
Removing leaf clocks from the clock framework for which the
current drivers lack support for the common clock framework.
The original approach was to add the complete clock tree and call
clk_prepare() and clk_enable() in the clock init routine, if the
driver does not yet do this.
The drawback of this approach is, that we also enable clocks, which
may be inactive on default (e.g. the peripheral is not connected on a
board and would be disabled by the bootloader). This may lead
to unnecessary power consumption.
With this patch all leaf clocks for which the driver does not
call clk_prepare() and clk_enable() are removed from the clock
framework leaving their gates untouched. Once a driver is ported
to use the common clock framework its leaf clocks must be readded.
John Linn [Thu, 23 Aug 2012 22:02:22 +0000 (15:02 -0700)]
Xilinx: ARM: update interrupts in device trees
The interrupt properties were using the wrong trigger type
and this corrects them. Most should be active high level.
The SCU devices are leading edge triggered and also have a
mask for the CPUs that can accept the interrupts.
Soren Brinkmann [Thu, 23 Aug 2012 07:53:29 +0000 (00:53 -0700)]
Xilinx: ARM: Skip delay calibration in hotplug path
Changing the CPU frequency while one core is offline
taints the offline CPU's loops per jiffy value.
With this patch delay calibration is skipped when returning
from hotplug and the correct lpj value from the master CPU
is used.
Suneel [Thu, 23 Aug 2012 13:22:09 +0000 (18:52 +0530)]
Xilinx: ARM: devcfg: Added support for partial bitstreams
This patch creates a syfs entry is_partial_bitstream to
indicate whether bitstream is partial or not. Based on the
value of is_partial_bitstream, PROG_B is asserted and
slcr_init_preload_fpga and slcr_init_postload_fpga functions
are invoked.
Registering a cpudile device for each core to allow both cores
to enter idle state.
Extending C1 state. C1 and C0 have the same functionality, but C1
implies more overhead and should be further extended to the proposed
sleep mode with RAM self-refresh.
Static initialization of the driver structure.
Timer uses common clock framework, which implies the following:
Timer init is done early during boot. To make clocks available through
COMMON_CLK clock init is called from irq_init() which is called with slab up
and before time_init(). Ugly, but works.
CPU frequency scaling messes up the time base. E.g. 'sleep x' does not sleep x
secionds but x scaled up by the factor the CPU is scaled down from its initial
frequency. I cannot find a way to adjust the clocksource/timekeeping to the
changing timer frequency. For this reason the clocksource in unregistered and
re-registered on frequency changes. See the comments in timer.c for more
details.
Soren Brinkmann [Wed, 27 Jun 2012 13:37:00 +0000 (06:37 -0700)]
Xilinx: ARM: Adding cpufreq support.
Adding cpufreq and OPP to mach-zynq in preparation for DVFS.
The current driver provides very simple frequency scaling functionality.
The whole code is based on OMAP's cpufreq driver.
Soren Brinkmann [Fri, 10 Aug 2012 13:01:41 +0000 (06:01 -0700)]
Xilinx: ARM: xi2cps: Port driver to COMMON_CLK
Use common clock framework to enable/disable i2c clocks in probe/remove
functions.
Add a clock notifier callback to adjust the i2c frequency when the i2c
input clock frequency changes due to cpu frequency scaling.
Soren Brinkmann [Fri, 22 Jun 2012 13:48:15 +0000 (06:48 -0700)]
Xilinx: ARM: xuartps: Updating set_baud_rate()
The original algorithm to find the best baud rate dividers does not necessarily
find the best set of dividers. And in the worst case may even write illegal
values to the hardware.
The new function should make better use of the hardware capabilities and be able
to provide valid settings for a wider range of baud rates and also input clocks.
Soren Brinkmann [Thu, 9 Aug 2012 12:51:07 +0000 (05:51 -0700)]
Xilinx: ARM: Zynq: Adding support for COMMON_CLK
Initial support for the common clock framework.
Added implemenatations modelling the PLLs and some of the peripheral clocks
in Zynq.
These implementations do not yet provide full functionality
Soren Brinkmann [Wed, 6 Jun 2012 13:47:09 +0000 (06:47 -0700)]
Xilinx: ARM: Prepare Kconfig for COMMON_CLK
Selecting Zynq as target architecture adds the common clock framework.
Selecting Zynq as target architecture was dependent on plat-versatile, which
lead to compile errors in combination with COMMON_CLK. Removing this dependency
fixes this issue.
Bryce Kellogg [Wed, 15 Aug 2012 21:24:56 +0000 (14:24 -0700)]
Xilinx: ARM: fixed board compatible in zc770 DC2 devicetree.
The DC2 device tree was declaring itself compatible with zc770
DC1. This is no longer true due to USB reset changes. The
compatible line has therefore been changed to the more generic
zynq-zc770.
Bryce Kellogg [Wed, 15 Aug 2012 21:18:21 +0000 (14:18 -0700)]
Xilinx: ARM: added Ethernet reset via GPIO on zc770 DC4.
The ethernet was being reset on DC4 the same way the USB was
being reset on zc70x and zc770 DC1. This fixes the ethernet by
toggling MIO7 in the boardfile.
Bryce Kellogg [Wed, 15 Aug 2012 17:34:19 +0000 (10:34 -0700)]
Xilinx: ARM: added USB reset via GPIO to zc770 and zc702.
A GPIO is toggled during board setup to reset the USB on the zc702
and zc770 DC1 boards. Because the same MIO is used for other things
on the other zc770 daughter cards, the zc770 board file contains
a check for the DC1 devicetree compatible string before toggling.
John Linn [Tue, 14 Aug 2012 21:07:25 +0000 (14:07 -0700)]
Xilinx: ARM: BSP: unlock SLCR in SMP boot
For now, the SLCR is being unlocked to allow power
management code to work. This should be reverted
once SLCR unlock/lock is centralized so that it is
locked by default and only unlocked when accessed.
John Linn [Tue, 7 Aug 2012 20:28:10 +0000 (13:28 -0700)]
Xilinx: ARM: BSP: clean up hotplug code
This is based on a patch from Soren during his clean
up. Change to the DSB instruction for clarity over CP15
operations. Use the correct bit for SMP in the Aux Control
Register. Use an explicit WFI also for clariy.
This allows the while hack to be removed such that it's
now working correctly.
John Linn [Thu, 2 Aug 2012 00:53:22 +0000 (17:53 -0700)]
Xilinx: ARM: remove initrd from device tree boot args
Now that bootm is being used in u-boot these are i
no longer needed and cause problems. The initrd is
needed if you are not booting the kernel from u-boot
(like from XMD) so you may need to add it back
in.
Xilinx: ARM: SWDT: fixed driver crash when interrupt not specified.
Previously the driver was not checking if the optional interrupt
parameters were in the devicetree and was trying to register
an interrupt handler no matter what. The driver has been changed
to only register an interrupt handler if the interrupt information
is present.
Xilinx: ARM: DMA: Handled Recoverable Errors in VDMA
There are some recoverable errors in AXI-VDMA, which are
DMA Internal Error, FSize Less Mismatch, LSize Less
Mismatch, FSize More Mismatch errors. When detected,
these errors need to be cleared (Write-on-Clear). And
these are only recoverable when C_FLUSH_ON_FSYNC is
enabled in hardware system.
This patch makes changes in the EmacPs interrupt handler to
clear the EmacPs interrupt status after processing a queued packet.
The status was getting cleared earlier immediately after entering
the interrupt handler. But since we try to process all available
BDs during processing of Txed/Rxed packets, it is better to clear
the interrupt status only after the BD processing is over. This
patch also puts appropriate barriers for reading/writing to registers.
Xilinx: ARM: EmacPs: Made changes to move/add proper spin_locks
The existing code had some potential issues for SMP case with
regards to spin lock handling. This patch fixes all such issues
and puts proper spin_locks (and unlocks) at appropriate places.
Xilinx: ARM: EmacPs: Ignore collisions for half duplex mode
For half duplex mode the collisions were being reported as errors.
For half duplex mode collisions are expected to occur for heavy
traffic and it is not an error case. Only when number of retries
exceeds the limit, then only it should be reported as an error.
This patch fixes the issue.
Xilinx: ARM: EmacPs: Fixed issues in Tx Timeout callback
The existing Tx timeout was not initializing the MAC with
correct speed and duplex settings. Because of this after
the Tx Timeout the MAC was failing to transmit and receive
ethernet traffic. This patch fixes this issue.
Xilinx: ARM: EmacPs: Made changes to reflect actual hardware registers
This patch removes hash defines for some of the register bit
fields that does not exist anymore with the current version
of hardware. This also makes changes in the code in view of the same.
Xilinx: ARM: DMA: Handled Recoverable Errors in VDMA
There are some recoverable errors in AXI-VDMA, which are
DMA Internal Error, FSize Less Mismatch, LSize Less
Mismatch, FSize More Mismatch errors. When detected,
these errors need to be cleared (Write-on-Clear). And
these are only recoverable when C_FLUSH_ON_FSYNC is
enabled in hardware system.
This patch makes changes in the EmacPs interrupt handler to
clear the EmacPs interrupt status after processing a queued packet.
The status was getting cleared earlier immediately after entering
the interrupt handler. But since we try to process all available
BDs during processing of Txed/Rxed packets, it is better to clear
the interrupt status only after the BD processing is over. This
patch also puts appropriate barriers for reading/writing to registers.
Xilinx: ARM: EmacPs: Made changes to move/add proper spin_locks
The existing code had some potential issues for SMP case with
regards to spin lock handling. This patch fixes all such issues
and puts proper spin_locks (and unlocks) at appropriate places.
Xilinx: ARM: EmacPs: Ignore collisions for half duplex mode
For half duplex mode the collisions were being reported as errors.
For half duplex mode collisions are expected to occur for heavy
traffic and it is not an error case. Only when number of retries
exceeds the limit, then only it should be reported as an error.
This patch fixes the issue.
Xilinx: ARM: EmacPs: Fixed issues in Tx Timeout callback
The existing Tx timeout was not initializing the MAC with
correct speed and duplex settings. Because of this after
the Tx Timeout the MAC was failing to transmit and receive
ethernet traffic. This patch fixes this issue.
Xilinx: ARM: EmacPs: Made changes to reflect actual hardware registers
This patch removes hash defines for some of the register bit
fields that does not exist anymore with the current version
of hardware. This also makes changes in the code in view of the same.
John Linn [Wed, 18 Jul 2012 21:53:58 +0000 (14:53 -0700)]
Xilinx: ARM: BSP: update memory initialization
This removes the reserving of memory for video and
also adds conditional compilation for the case where
the memory is not at 0 so as not to hang the kernel.