Holden Sandlar [Tue, 7 Nov 2017 05:35:23 +0000 (11:05 +0530)]
spi: zynqmp-gqspi direct read made word aligned.
in gqspi driver direct read is updated with the word aligned read.
For reading file which is not page aligned word aligned read is
required in IO mode, DMA mode handles this by default.
Michael Gill [Tue, 31 Oct 2017 18:26:52 +0000 (11:26 -0700)]
staging: apf: Fix warnings in apf drivers
This is a small patch to address a number of compiler warnings
and style problems in the apf drivers. No features or functional
changes are associated with this patch.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
in gqspi driver direct read is updated with the word aligned read.
For reading file which is not page aligned word aligned read is
required in IO mode, DMA mode handles this by default.
Signed-off-by: Tejas Prajapati Rameshchandra <tejaspra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd nand oob test gives reset to nand device at the start.
This will be problem for the nand devices which are configured for
nvddr modes. i.e controller and device both are not is same mode,
resulting failure in mtd-oob test. this patch fixes this with out
issuing reset.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fixed regression introduced by remove volatile in
'a920e66a043 ("char: xilinx_devcfg: Fix warnings in the driver")'
removed volatile around dma_done and error_status without further actions.
This fix prevents these variables from being optimized away without being
read.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Saurabh Sengar [Fri, 20 Oct 2017 11:55:56 +0000 (17:25 +0530)]
drm: xilinx: sdi: adding psf mode support
Adding Progressive Segmented Frame support in sdi Tx driver.
For psf modes, input should be double the output framerate
For 30 psf output, input vrefresh should be 60
For 25 psf output, input vrefresh should be 50
For 24 psf output, input vrefresh should be 48
device_config[31:30] in MSTR register of ddrc Indicates the configuration
of the device used in the system as follows
- 00 - x4 device
- 01 - x8 device
- 10 - x16 device
- 11 - x32 device
for x16 and x32, instead of 2 and 3 we added 0x10 and 0x11 which is wrong.
This patch corrects these macro defines.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Saurabh Sengar [Mon, 16 Oct 2017 13:02:33 +0000 (18:32 +0530)]
drm: xilinx: sdi: omnitek box modes
Tested with new sdi compliance Omnitek box.
Based on this box modifying SDI DRM_MODE table.
Adding the support for below new modes:
- 1920x1080i@48
- 2048x1080i@48
- 2048x1080i@50
- 2048x1080i@60
- 1920x1080@48
- 3840x2160@48
Correcting 3 other resolutions value as well observed
while testing.
- 1920x1080i@50
- 4096x2160@48Hz
- 1920x1080i@96Hz
Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Saurabh Sengar [Fri, 13 Oct 2017 10:12:57 +0000 (15:42 +0530)]
drm: xilinx: vtc: removing hard coded values for signal polarity
removing hard coded values for following signal polarity parameters,
and taking from vm.flags instead.
This will help clients driver to program signal polarity as per
drivers need.
This patch fixes the below sparse warning in the driver
drivers/dma/xilinx/xilinx_dma.c: In function ‘xilinx_vdma_dma_prep_interleaved’:
drivers/dma/xilinx/xilinx_dma.c:1589:43: warning: variable ‘prev’ set but not used [-Wunused-but-set-variable]
struct xilinx_vdma_tx_segment *segment, *prev = NULL;
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dma: xilinx: axidmatest: Fix race conditions in the test client
This patch does the below
--> Test client is limiting the test buffer size to 700
remove the check for the same also this patch increases the
default value of test buf size from 64 to 16k.
--> Terminate the existing transactions before freeing the dma channel.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dma: xilinx: Fix race conditions in the driver for cdma
This patch fixes the below issues
--> when hardware is idle we need to toggle the SG bit
inorder to update new value to the current descriptor
register other wise undefined results will occur.
--> Halt bit is not valid for cdma case add checks
for the same.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mousumi Jana [Thu, 12 Oct 2017 11:33:11 +0000 (17:03 +0530)]
can: xilinx: proper acknowledgment of ISR Flags.
This patch adds the correct acknowledgment of the
ISR Flags. Previously all the bitflags are used to
acknowledge all kind of interrupts.But now required
flags are acknowledged.
Signed-off-by: Mousumi Jana <mousumij@xilinx.com> Reviewed-by: Kedareswara Rao appana<appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Wed, 11 Oct 2017 00:26:39 +0000 (17:26 -0700)]
drm: xilinx: dp: Skip the aux communication when there's no sink
The DRM master may request the aux transaction, for example, power off
request, even when the sink is not connected. This would result in
the timeout. The connection status is stored in the HPD handler
and checked before the aux transaction.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
in nor_write, we need to say back to upper layers about how much
data we transferred. there is a bug in this logic while updating the
number of bytes written. this patch fixes this issue. the existing logic
is not checking for last page and from there onwards we are running into
issues while updating the written bytes.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vishal Sagar [Mon, 9 Oct 2017 05:48:47 +0000 (11:18 +0530)]
v4l: xilinx: sdirxss: Add v4l control for transport stream type
Add v4l control to get the transport stream type as interlaced
or progressive. In case ST352 payload is not available, fallback
to detecting the transport type from the rx_t_scan bit.
Vishal Sagar [Mon, 9 Oct 2017 05:48:46 +0000 (11:18 +0530)]
v4l: xilinx: sdirxss: Add support for subdev get frame interval
Add support to get the subdev frame interval from ST352 payload.
The numerator is either 1000 or 1001 for integral or fractional fps.
The denominator is actual fps * 1000.
Leon Luo [Fri, 6 Oct 2017 16:23:48 +0000 (09:23 -0700)]
imx274: V4l2 driver for Sony imx274 CMOS sensor
The imx274 is a Sony CMOS image sensor that has 1/2.5 image size.
It supports up to 3840x2160 (4K) 60fps, 1080p 120fps. The interface
is 4-lane MIPI CSI-2 running at 1.44Gbps each.
This driver has been tested on Xilinx ZCU102 platform with a Leopard
LI-IMX274MIPI-FMC camera board.
Support for the following features:
-Resolutions: 3840x2160, 1920x1080, 1280x720
-Frame rate: 3840x2160 : 5 – 60fps
1920x1080 : 5 – 120fps
1280x720 : 5 – 120fps
-Exposure time: 16 – (frame interval) micro-seconds
-Gain: 1x - 180x
-VFLIP: enable/disabledrivers/media/i2c/imx274.c
-Test pattern: 12 test patterns
Signed-off-by: Leon Luo <leonl@leopardimaging.com> Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
(cherry picked from commit 9216969e80c0b87b164ffd827b17471e769aad99) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Leon Luo [Fri, 6 Oct 2017 16:23:47 +0000 (09:23 -0700)]
imx274: device tree binding file
The binding file for imx274 CMOS sensor V4l2 driver
Signed-off-by: Leon Luo <leonl@leopardimaging.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
(cherry picked from commit 49b4f20dbe4bd17d9f1b22bf0b481fe4c2d2ca83) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/clk/zynqmp/clkc.c:155:20: warning: 'usb0_mio_mux_parents'
defined but not used [-Wunused-variable]
static const char *usb0_mio_mux_parents[] __initconst = {usb0_bus_ref,
^
drivers/clk/zynqmp/clkc.c:157:20: warning: 'usb1_mio_mux_parents'
defined but not used [-Wunused-variable]
static const char *usb1_mio_mux_parents[] __initconst = {usb1_bus_ref,
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynqmp: devicetree: Add no-1-8-v property to sdhci1 node
This patch adds no-1-8-v property to sdhci1 node such that SD operates
at 50MHz by default. To operate at UHS mode, this property can be
removed from the sdhci1 node.
Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
misc: xilinx-sdfec: initial driver support for xilinx sdfec
This commit adds a char driver for SDFEC (Soft Decision FEC) IP.
The Forward Error Correction(FEC) Engine is a Hard IP block which
provides high throughput LDPC and Turbo Code implementations.
Some of the driver design decisions were based on the following
hardware behaviour:
- In-band reset register was not present. External reset
being provisioned depends on system designer. Driver
needs to be notified of a reset by ioctl.
- Codes cannot be updated on the fly and codes can be large.
Codes are marshalled via ioctl to setup the device.
- Interrupts indicate a failure of the SDFEC instance
Signed-off-by: Rohit Athavale <rohit.athavale@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
soc: zynqmp: Added pm api functions for RSA, SHA and AES
This patch adds PM APIs to provided access to xilsecure
library to calculate SHA3 hash on the data or to encrypt
or decrypt the data using AES hardware engine and to
encrypt or decrypt the data by using RSA public or private
keys respectively.
Signed-off-by: Durga Challa <vnsldurg@xilinx.com> Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch does the following cleanup to keep master in
sync with rebase branch:
- Correct comment style in one place
- Correct coding style when using case in one place
- Remove repeated code for setting DMA mask in the probe
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The FW (xilfpga) is using single pair of keys to authenticate the
Image. According to the xilinx flow we need to use a pair of
keys to provide the proper authentication support.
currently the FW don't have this support. So this patch
remove the Authenticated BitStream loading support.
Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This file was changed in past because of TRD but it wasn't tested over
time that's why several merges between probably breaks it.
Changes which were done are already integreated in this kernel that's
why this syncup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: phy: Fix mask value write on gmii2rgmii converter speed register
To clear Speed Selection in MDIO control register(0x10),
ie, clear bits 6 and 13 to zero while keeping other bits same.
Before AND operation,The Mask value has to be perform with bitwise NOT
operation (ie, ~ operator)
This patch clears current speed selection before writing the
new speed settings to gmii2rgmii converter
Following issues are being observed when SMMU is
enabled,
- After suspend/resume with FPD off,all peripherals
registered with SMMU are failed to work.
- SATA device detection is failed
Disabling SMMU till said issues are fixed.
Rajan Vaja [Mon, 28 Aug 2017 09:13:57 +0000 (02:13 -0700)]
ARM64: zynqmp: Do not set requirements to 0 for wakeup sources
Devices which are set as wakeup source or belongs to wakeup
source device's path should not be powered off by generic power
domain driver.
Add check in zynqmp GPD power off function to check if device
is in wakeup source path. If so, set capabilities to WAKEUP
instead of 0 in GPD power off function.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dma: xilinx: Fix issues with vdma mulit fstore configuration
This commit
ie: 'commit 4f143cb03aba ("dmaeninge: xilinx_dma: Fix bug in multiple
frame stores scenario in vdma")'
fixes issues with multiple fstore by using circular mode feature.
This implementation has a limitation as user needs to enable a hidden
configuration option(c_debug_all) in the IP while creating the design.
If user not aware of this h/w option and submits more frames
then driver throughs a warning asking to enable the
hidden configuration option.
This patches fixes these issues by using the park mode feature.
With this patch driver continuously parks through frame buffers
based on the number of frames user submitted.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Some monitors require delay to fully wake up. Otherwise, it may
result in some error such as training failure.
Delay of 4 msec was not specified in the spec, but found from
experimentation (ex, no failure for 20 times or more). Thus,
this setting is exposed as module parameter so that user can
change if needed.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dma: xilinx: Add private API to permit retrieval of supported mem formats
The video Framebuffer DMA IP requires clients to send a fourcc code
to indicate the memory format layout. The IP can be configured to support
a variety of memory formats ranging from YUYV, RGB and in either 8 bit
or 10 bit formats. There has been no method for clients to obtain
this list of supported formats. This patch adds private APIs that
can be called from clients to retrieve this list so that user space
applications can choose from any of the available memory formats.
Depends on patch 13fd162 (dma: xilinx: Bug fix to ensure only video formats
enabled in IP are in driver)
Hyun Kwon [Wed, 30 Aug 2017 22:05:44 +0000 (15:05 -0700)]
drm: xilinx: dp: Enable the training pattern transmission early
Per DP v1.2 spec 3.5.1.2.2, the transmission of training pattern
needs to be enabled before setting the sink device. This sequence
was causing the failure of initial training attempt, thus, enable
the pattern in the controller before setting the sink through aux.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Manish Narani [Wed, 30 Aug 2017 06:34:16 +0000 (12:04 +0530)]
zynq: devicetree: Remove 'broken-adma2' property
This patch removes 'broken-adma2' property from the zynq device-tree.
This basically enables the use of ADMA instead of SDMA. With the latest
kernel the ADMA is working fine in SD so no need to use the SDMA which
is slower than ADMA.
Fixed by : 7c415150cdd6 ("ARM: zynq: Reserve correct amount of non-DMA RAM")
Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jeffrey Mouroux [Tue, 29 Aug 2017 01:12:45 +0000 (18:12 -0700)]
dma: xilinx: Bug fix to ensure GPIO is reset between DMA operations
Some registers within the Video Framebuffer driver, such as the
video format register, require a reset of the IP before they can
be altered. Because there is no software accessible reset register,
an external GPIO is used. This patch fixes a runtime issue wherein
clients wish to reprogram the IP for a new memory between DMA operations.
Without this fix, the Video Framebuffer Write IP may halt when a client
requests a new DMA operation using a different memory format for
writes to host memory. In some cases, Framebuffer Read operations
will need to be reset when the downstream video pipeline is being
reset.
Saurabh Sengar [Tue, 29 Aug 2017 06:32:57 +0000 (12:02 +0530)]
drm: sdi: xilinx: correcting multi link payload value
Channel bit have to be set only in case of multi link data.
In SDI-TX logicore IP, except 3GB mode all other modes are
single link only, hence these bit is redundant.
3GB mode is dual link.
For 3GB mode first link have to be programmed as channel 1,
and second link payload have to be programmed as channel 3.
Mubin Sayyed [Thu, 31 Aug 2017 05:56:06 +0000 (11:26 +0530)]
arm64: zynqmp: Add back stream-id-cells property for lpd-dma
stream-id-cells property is mandatory for SMMU driver over xen,
so adding it back to all lpd-dma-channels.
Since just removing "iommus" property suffice to bypass SMMU over
native linux,SMMU would be still bypassed for lpd-dma over linux.
Signed-off-by: Mubin Sayyed <mubinusm@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drm: xilinx: plane: Don't cache the property values
Some of these properties need to be updated as hardware values
don't get restored to the default values. Thus, don't cache
the values, but update those when there's request.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The present logic doesn't fetch the correct parent node when two usb nodes
are enabled. It searches all nodes and doesn't fetch the first node with
matching compatible string when two usb nodes are enabled.
This patch fixes the logic by searching "xlnx,zynqmp-dwc3" compatible
string only in the parent nodes instead of the searching all nodes.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: qspi: Corrected the sequence for accessing flash part
For accessing flash part using the mtd devices for architectures which
only supports 3 byte addressing need to call write_ear() for accessing
memory above 16MB. After every call to write_ear(), write_enable()
has to be called for further process.
Signed-off-by: Tejas Prajapati Rameshchandra <tejaspra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jeffrey Mouroux [Mon, 28 Aug 2017 21:56:54 +0000 (14:56 -0700)]
Bug fix to ensure only video formats enabled in IP are in driver
The driver used to assume that all IP supported video formats were
legal choices for configuration. However, the IP can be configured
to support all or only some (or only one) of the many possible formats.
This patch adds the needed mechanism via device-tree to communicate to
the driver which video formats are actually supported in the IP.
Additional changes are required to ensure that DMA client requests
for video formats that are NOT supported by the device instance are
rejected.
Jeffrey Mouroux [Mon, 28 Aug 2017 21:56:53 +0000 (14:56 -0700)]
Documentation: devicetree: bindings: dma: New dts property
A new device tree property is described that will describe
the video formats supported in the Video Framebuffer DMA device.
The Video Framebuffer IP is configurabe and can be configured with
varying support for a number of possible video memory formats in
an effort to tailor the size of the logic footprint. The driver
will utilize this new device tree property to describe this
configuration.
projects / zynq / linux.git / log