Hyun Kwon [Tue, 6 May 2014 02:52:27 +0000 (19:52 -0700)]
drm: adv7511: Add the rgb format flag to adv7511_link_config
Add the rgb format boolean flag to struct adv7511_link_config. This was in
the drm encoder driver, but having it in the adv7511 driver would remove
direct dependency. The flag is copied to the struct adv7511 to be used for
the transmitter configuration.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Only insert a delayed disconnected event when we transition from connected to
connect. If we transition from disconnected to connected there is no need for
this since the system will already assume that the monitor was disconnected.
DRM: adv7511: Properly initialize dpms_mode and status
Set dpms_mode to DRM_MODE_DPMS_OFF and status to connector_status_disconnected
to make sure that they match the state of the chip. This fixes an issue where
the monitor was incorrectly reported as disconnected during cold boot.
Harini Katakam [Mon, 5 May 2014 09:33:14 +0000 (15:03 +0530)]
spi: zynq-qspi: Dont write more than requested bytes to rxbuf
In case of dual parallel odd byte transfer, write even bytes and
read bytes accordingly but write only the requested number of bytes to rxbuf.
Otherwise any user data adjacent to rxbuf might be corrupted.
Improve related comments.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Thu, 1 May 2014 16:36:39 +0000 (09:36 -0700)]
ARM: zynq: Synchronise zynq_cpu_die/kill
Avoid races and add synchronisation between the arch specific
kill and die routines.
The same synchronisation issue was fixed on IMX platform
by this commit:
"ARM: imx: fix sync issue between imx_cpu_die and imx_cpu_kill"
(sha1: 2f3edfd7e27ad4206acbc2ae99c9df5f46353024)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Thu, 1 May 2014 16:36:36 +0000 (09:36 -0700)]
ARM: zynq: Remove redundant code from hotplug
When secondary cores are hotplugged, their reset gets asserted and cache
operations are handled in the core. Due to most of the Zynq's
arch-specific hotplug code can be removed.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add xilinx compatible string along with cadence.
Compatible string should be first in the node.
Make num-cs optional property.
Add is-decoded-cs property.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:07 +0000 (14:59 +0530)]
spi: cadence: Chip select related changes
Change chip select property name to "num-cs". Use a default value
instead of giving error when num-cs is not found.
Add "is-decoded-cs" property for using extended slave select; make
necessary changes in cdns_spi_chipselect function.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:06 +0000 (14:59 +0530)]
spi: cadence: Suspend/Resume cleanup
Remove use of driver state in probe, suspend, resume and prep_transfer_hw.
Just call master suspend/resume and disable_unprepare or prepare_enable clocks
as required in suspend/resume.
Remove debug prints in suspend/resume.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:05 +0000 (14:59 +0530)]
spi: cadence: setup cleanup
Make CPOL/CPHA configuration a separate function. Since these dont vary
between transfers and need to be set when preparing hw before enabling spi,
call from prep_transfer_hw.
Remove spi_setup as this is no longer required.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:04 +0000 (14:59 +0530)]
spi: cadence: Use transfer_one hook
Implement transfer_one and set_cs functions. Change initialization, completion
and irq handling accordingly. Remove timeout check as core does this.
Remove reset function as it is no longer used.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:03 +0000 (14:59 +0530)]
spi: cadence: Make register read and write operations static inline functions
Make cdns_spi_read and cdns_spi_write static inline functions which
take driver instance pointer, offset, data as inputs and perform necessary
read/write operation.
Modify init_hw function to pass instance pointer instead of register base address.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:02 +0000 (14:59 +0530)]
spi: cadence: irq related cleanup
Request irq after init_hw in probe.
Check for irq<=0 as 0 is also considered error condition.
Return IRQ_HANDLED only when interrupt is handled, otherwise return IRQ_NONE.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 May 2014 09:29:00 +0000 (14:59 +0530)]
spi: cadence: Use max speed checks in the core
Set master->max_speed_hz to let core perform necessary checks.
Remove checks in the driver.
If transfer speed is requested as zero after checks in the core,
dont set max speed, default to min speed.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 5 May 2014 14:03:55 +0000 (16:03 +0200)]
tty: serial: uartlite: Specify time for sending chars
Xilinx MDM (Microblaze Debug Module) also contains
uart interface via JTAG which is compatible with
uartlite driver. This interface is really slow
that's why timeout is setup to 1s.
Make this time delay not to be cpu speed dependent.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
media: xilinx: dma: Stop entity chain walk at the entity with no sink pad
When starting or stopping the pipeline, the pipeline driver walks
the entities chain, and starts or stops all of them. When the walk reaches
the entity with no sink pad, walk needs to stop. xvip_get_entity_sink()
returns either the valid sink pad, or NULL when the entity doesn't have any
sink pad. When NULL is returned, stop the walk.
drm: i2c: adv7511: Initialize the DPMS value in adv7511_probe()
Initialize the DPMS value to DRM_MODE_DPMS_OFF in adv7511_probe() function.
Otherwise, the value is set to DRM_MODE_DPMS_ON(=0) which doesn't reflect
the actual device's DPMS state. This also results in not turning on
the device properly.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drm: xilinx: drv: Set bpp and color depth to drm_framebuffer
The drm crtc helper doesn't set bpp and color depth for non RGB format
drm_framebuffer, and that results in not supporting YUV format planes
properly. This patch fixes and the YUV format drm_framebuffer can be allocated
and used for planes.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drm: xilinx: drv: Add color depth info to the format descriptor
Add color depth info to the the format descriptor. xilinx_drm_format_depth()
can be used to retrieve the color depth value corresponding to the given drm
format code.
Signed-off-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 18 Mar 2014 16:18:13 +0000 (09:18 -0700)]
media: xilinx: dma: Change vdma configuration to cyclic-mode
VDMA in non-cyclic mode doesn't work with fsync enabled. Fsync is needed
to synchronize the pipeline with external input. So VDMA is configured to
cyclic mode in this patch, with fsync enabled at synthesis. This patch is
the only way to run the pipeline with external input, and it will be
revisited after IP level investigation.
net: xilinx_emacps: Release receive BDs when there is a resource error
Driver should clean/release the BDs when it detects a resource error to
ensure the proper cleanup and allow the controller to recover from rx
lockdown issue.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynq-qspi: Changes to support dual parallel in new driver implementation
This patch implements support for dual parallel on top of the recent changes
to qspi driver which implements transfer->one.
In parallel configuration, all commands are sent to both flash devices but
the data is split into odd and even bits between lower and upper flash.
As a result of this data should be of even length for write/read operations.
For Ex.,
A program operation for 3 bytes will ideally be:
CMD + 3 ADDR BYTES + 3 DATA BYTES
In dual parallel case, this means 8 + 24 + (3*8/2) = 44 clock cycles will be sent.
From the flash perspective, it only received 1 and 1/2 bytes' cycles.
To avoid this error, when odd number of data bytes are asked to be transmitted,
an extra byte is sent to compensate for the nibble flash devices will be expecting.
Checks for bytes_to_receive/transmit < 0 were removed where not required.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
In the changed m25p80.c from mainline, quad read opcode is set based on
flags in device table. This also takes care of dummy bytes. Make use of this.
Added this flag to all devices known to support quad read.
Updated m25p80.c from mainline calls spansion_quad_enable by default
when quad mode is supported. This command is only required (supported)
for spansion and winbond. Even in that case, it's a non-volatile setting.
This implementation is not guaranteed to work when flash devices are
connected in parallel/stacked configuration.
Hence remove it and revisit if required.
Updated m25p80.c from mainline uses "mode" in spi device structure to
select quad read. This, in turn, is set by spi core based on dts properties.
Hence, update tx and rx bus width in dts for above purpose.
The flags M25P80_QUAD_READ and SECT_32 both have the same value - correct this.
Remove unused variables in flash structure.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add configuration of U_PAGE/L_PAGE before asserting chip select.
(This was removed earlier when subsystem workqueue, set_cs and transfer_one
hooks were used)
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The existing timeout value in wait_for_completion_timeout is
calculated from the transfer length and speed with tolerance of 10msec.
This is too low because this is used for error conditions such as
hardware hang etc.
The xfer->speed_hz considered may not be the actual speed set
because the best clock divisor is chosen from a limited set such that
the actual speed <= requested speed. This will lead to timeout being
less than actual transfer time.
Considering acceptable latencies, this timeout can be set to a
value double the expected transfer plus 100 msecs.
This patch adds the same in the core.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Mark Brown <broonie@linaro.org>
clocksource/cadence_ttc: Adjust timer frequency on clock changes
Implement a clock notifier to handle changes of the timer's input clock
frequency.
This syncs up the driver with mainline squashing the following commits
into this one:
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
clocksource/cadence_ttc: Call clockevents_update_freq() with IRQs enabled
The timer core takes care of serialization and IRQs. Hence the driver is
no longer required to disable interrupts when calling
clockevents_update_freq().
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
(cherry picked from commit 5f0ba3b462b2d36b3c28748863747fb1050f40d0)
clocksource/cadence_ttc: Overhaul clocksource frequency adjustment
The currently used method adjusting the clocksource to a changing input
frequency does not work on kernels from 3.11 on.
The new approach is to keep the timer frequency as constant as possible.
I.e.
- due to the TTC's prescaler limitations, allow frequency changes
only if the frequency scales by a power of 2
- adjust the counter's divider on the fly when a frequency change
occurs
This limits cpufreq to scale by certain factors only.
But we may keep the time base somewhat constant, so that sleep() & co
keep working as expected, while supporting cpufreq.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
(cherry picked from commit b3e90722f6f53fa457a88146a877e34ea71d25ea)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
clockevents: Adjust timer interval when frequency changes
clockevent devices in periodic mode are not updated when the frequency
of the device changes. Issue a dev->set_mode() callback which forces
the device to reevaluate the timer settings.
Thomas Gleixner [Fri, 11 Apr 2014 16:24:01 +0000 (09:24 -0700)]
clockevents: Serialize calls to clockevents_update_freq() in the core
We can identify the broadcast device in the core and serialize all
callers including interrupts on a different CPU against the update.
Also, disabling interrupts is moved into the core allowing callers to
leave interrutps enabled when calling clockevents_update_freq().
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Soeren Brinkmann <soren.brinkmann@xilinx.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Michal Simek <michal.simek@xilinx.com> Link: http://lkml.kernel.org/r/1391466877-28908-2-git-send-email-soren.brinkmann@xilinx.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
(cherry picked from commit 627ee7947e2e83ba565c31c5c9373d6e364b1ecd) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use the name pclk instead of aper_clk and change the variable name accordingly.
Change variable name from devclk to refclk just for clarity.
Changes made in driver and relevant dts.
Timeouts are purely handled in SW using completions. All accesses to the
timeout register and the timeout IRQ can be removed.
Also, sync the timeout durations with mainline.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynq-qspi: Check for busy in setup and call setup_transfer
In setup, call setup transfer to ensure clock configuration is done
before spi is enabled.
Check for busy so as to not interrupt existing transfer with this config.
This is necessary as clock config needs to happen before when disabled.
The current transfer_one hook used will not allow the earlier flow of
disabling and enabling.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rename num-chipselect property to the commonly used num-cs.
When reading num-cs read into temporary u32 variable and then
copy to master->num_chipselect which is u16.
When num-cs is not present, use a default value instead of
returning error.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynq-qspi: Clean up zynq_qspi_read/copy_data functions
Use memcpy to simplify qspi_read/copy_data funcitons.
Part of these changes were done by Thomas Betker but are also
included in this series as there were futher changes done on top of it.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove flash command table as driver need not check for the command
and write to TXD based on that.
This was fixed by Thomas Betker in his patches but the same was also
included in this series as further changes were made on top.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Changed Xylon DRM crtc structure variable name which contains private
plane id to be named in the same style as drm_plane structure private plane
pointer.
Signed-off-by: Davor Joja <davorjoja@logicbricks.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
gpu: drm: xylon: Fixed variable and function argument types
Fixed Xylon DRM logicvc main structure variable types according to its usage
and sorted accordingly.
Fixed function argument type to be as hw register width.
Signed-off-by: Davor Joja <davorjoja@logicbricks.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx.
The XADC has a DRP interface for communication. Currently two different
frontends for the DRP interface exist. One that is only available on the ZYNQ
family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
on all series 7 platforms and is a softmacro with a AXI interface. This driver
supports both interfaces and internally has a small abstraction layer that hides
the specifics of these interfaces from the main driver logic.
The ADC has a couple of internal channels which are used for voltage and
temperature monitoring of the FPGA as well as one primary and up to 16 channels
auxiliary channels for measuring external voltages. The external auxiliary
channels can either be directly connected each to one physical pin on the FPGA
or they can make use of an external multiplexer which is responsible for
multiplexing the external signals onto one pair of physical pins.
The voltage and temperature monitoring channels also have an event capability
which allows to generate a interrupt when their value falls below or raises
above a set threshold.
Buffered sampling mode is supported by the driver, but only for AXI-XADC since
the ZYNQ XADC interface does not have capabilities for supporting buffer mode
(no end-of-conversion interrupt). If buffered mode is supported the driver will
register two triggers. One "xadc-samplerate" trigger which will generate samples
with the configured samplerate. And one "xadc-convst" trigger which will
generate one sample each time the CONVST (conversion start) signal is asserted.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
projects / zynq / linux.git / log