drivers/uio/uio_xilinx_apm.c: In function 'xapm_probe':
drivers/uio/uio_xilinx_apm.c:283:24: warning: passing argument 1 of 'clk_disable_unprepare' from incompatible pointer type
clk_disable_unprepare(&xapm->param.clk);
^
In file included from drivers/uio/uio_xilinx_apm.c:26:0:
include/linux/clk.h:482:20: note: expected 'struct clk *' but argument is of type 'struct clk **'
static inline void clk_disable_unprepare(struct clk *clk)
^
drivers/uio/uio_xilinx_apm.c: In function 'xapm_remove':
drivers/uio/uio_xilinx_apm.c:298:24: warning: passing argument 1 of 'clk_disable_unprepare' from incompatible pointer type
clk_disable_unprepare(&xapm->param.clk);
^
In file included from drivers/uio/uio_xilinx_apm.c:26:0:
include/linux/clk.h:482:20: note: expected 'struct clk *' but argument is of type 'struct clk **'
static inline void clk_disable_unprepare(struct clk *clk)
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 21 Jul 2016 14:49:27 +0000 (16:49 +0200)]
Merge tag 'v4.6' into master
Fix issues in spi-nor driver.
Fix xilinx_phy compilation:
net: phy: xilinx_phy: Fix compilation errors in the driver
This commit e5a03bfd873c ("phy: Add an mdio_device structure")
modifies the phydev strcture fields.
This patch updates for the same in the driver
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Apply revert of:
"kbuild: Add option to turn incompatible pointer check into error"
(sha1: ea8daa7b97842aab8507b5b5b1e3226cf2d514a6).
because some drivers are causing compilation warnings.
Apply this patch when compilations warnings are fixed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The MALI driver will be included through PetaLinux / Yocto as
a off-tree module. Thus, the driver should be disabled in the branch
as default to avoid conflict.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
reset: Updated the Kconfig file for zynqmp reset-controller
The zynqmp reset controller needs Power Management API's to complete
the actual task. So this patch updates the Kconfig file with required PM
dependencies to avoid the compilation errors.
Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dma: xilinx: dpdma: Support multi-channel operations
In case of mult-planar formats, multiple video channels should
be operated in sync. For this, introduce the video group, which
guarantees all relevant channels are triggered / pasued at
the same time.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The zynqmp_dmatest is replicate of dmatest client
except to test scatter gather mode.
Now the support for scatter gather mode also got
added to dmatest client so no need of this driver.
This patch fixes the below static checker warning
drivers/dma/xilinx/zynqmp_dma.c:973 zynqmp_dma_chan_probe()
warn: was && intended here instead of ||?
Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
dmaengine: xilinx: Use different channel names for each dma
Current driver assumes that child node channel name is either
"xlnx,axi-vdma-mm2s-channel" or "xlnx,axi-vdma-s2mm-channel"
which is confusing the users of AXI DMA and CDMA.
This patch fixes this issue by using different channel
names for the AXI DMA and AXI CDMA child nodes.
dmaengine: vdma: Add support for mulit-channel dma mode
This patch adds support for AXI DMA multi-channel dma mode
Multichannel mode enables DMA to connect to multiple masters
and slaves on the streaming side.
In Multichannel mode AXI DMA supports 2D transfers.
dmaengine: vdma: Add 64 bit addressing support for the axi cdma
The AXI CDMA is a soft ip, which can be programmed to support
32 bit addressing or greater than 32 bit addressing.
When the AXI CDMA ip is configured for 32 bit address space
in simple dma mode the source/destination buffer address is
specified by a single register(18h for Source buffer address and
20h for Destination buffer address). When configured in SG mode
the current descriptor and tail descriptor are specified by a
Single register(08h for curdesc 10h for tail desc).
When the AXI CDMA core is configured for an address space greater
than 32 then each buffer address or descriptor address is specified by
a combination of two registers.
The first register specifies the LSB 32 bits of address,
while the next register specifies the MSB 32 bits of address.
For example, 08h will specify the LSB 32 bits while 0Ch will
specify the MSB 32 bits of the first start address.
So we need to program two registers at a time.
This patch adds the 64 bit addressing support to the axicdma
IP in the driver.
dmaengine: vdma: Add 64 bit addressing support for the axi dma
The AXI DMA is a soft ip, which can be programmed to support
32 bit addressing or greater than 32 bit addressing.
When the AXI DMA ip is configured for 32 bit address space
in simple dma mode the buffer address is specified by a single register
(18h for MM2S channel and 48h for S2MM channel). When configured in SG mode
The current descriptor and tail descriptor are specified by a single
Register(08h for curdesc 10h for tail desc for MM2S channel and 38h for
Curdesc and 40h for tail desc for S2MM).
When the AXI DMA core is configured for an address space greater
than 32 then each buffer address or descriptor address is specified by
a combination of two registers.
The first register specifies the LSB 32 bits of address,
while the next register specifies the MSB 32 bits of address.
For example, 48h will specify the LSB 32 bits while 4Ch will
specify the MSB 32 bits of the first start address.
So we need to program two registers at a time.
This patch adds the 64 bit addressing support for the axidma
IP in the driver.
The newly added xilinx_dma_prep_dma_cyclic function sometimes causes
a gcc warning about the use of the segment function in case
we never run into the inner loop of the function:
dma/xilinx/xilinx_vdma.c: In function 'xilinx_dma_prep_dma_cyclic':
dma/xilinx/xilinx_vdma.c:1808:23: error: 'segment' may be used uninitialized in this function [-Werror=maybe-uninitialized]
segment->hw.control |= XILINX_DMA_BD_SOP;
This can only happen if the period len is zero (which would cause other
problems earlier), or if the buffer is shorter than a period. Neither
of them should ever happen, but by adding an explicit check for these two
cases, we can abort in a more controlled way, and the compiler is
able to see that we never use uninitialized data.
dmaengine: vdma: Fix compilation warning in cyclic dma mode
This patch fixes the below compilation warining.
drivers/dma/xilinx/xilinx_vdma.c: In function 'xilinx_dma_prep_dma_cyclic':
drivers/dma/xilinx/xilinx_vdma.c:1808:23: warning: 'segment' may be used
uninitialized in this function [-Wmaybe-uninitialized]
segment->hw.control |= XILINX_DMA_BD_SOP;
The start of packet (SOP) should be set to the first segment in the desc
chain not for the last segment of the desc chain.
This patch adds support for AXI DMA cyclic dma mode.
In cyclic mode, DMA fetches and processes the same
BDs without interruption. The DMA continues to fetch and process
until it is stopped or reset.
dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine
This patch adds support for the AXI Central Direct Memory Access
(AXI CDMA) core to the existing vdma driver, AXI CDMA is a
soft Xilinx IP core that provides high-bandwidth
Direct Memory Access(DMA) between a memory-mapped
source address and a memory-mapped destination address.
dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine
This patch adds support for the AXI Direct Memory Access (AXI DMA)
core in the existing vdma driver, AXI DMA Core is a
soft Xilinx IP core that provides high-bandwidth
direct memory access between memory and AXI4-Stream
type target peripherals.
Michael Gill [Tue, 12 Jul 2016 18:37:19 +0000 (11:37 -0700)]
staging: apf: Fix address calculation for SG-DMA transfers
If a buffer allocated with the use of sds_alloc is used in an
SG-DMA transfer such that only the end of the buffer is
transferred, the address calculation needed to skip the beginning
of the buffer was incorrect. This patch fixes that issue.
dma: xilinx: axidma: Fix race condition in the cyclic dma mode
This patch fixes below race conditions in the cyclic dma mode.
---> In cyclic dma mode we need to configure tail bd pointer
to a value which is not part of bd chain.
---> Link the tail bd segment with the head bd segment
in cyclic dma mode.
dma: xilinx: zynqmp_dma: Fix race condition in the driver
In the driver software descriptor pools are allocated only when
SG is enabled in the driver. but we are freeing the desc polls in
Simple dma mode case also which is causing kernel crash when running
The dmatest client multiple times this patch fixes this issue.
P L Sai Krishna [Fri, 1 Jul 2016 12:48:21 +0000 (18:18 +0530)]
mtd: spi-nor: Added support for n25q00a.
This patch adds support for Micron n25q00a part by
adding in spi_nor_ids table.
This part is different from n25q00 in Memory Type Byte.
Memory Type for n25q00 - BAh
Memory Type for n25q00a - BBh
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Mon, 27 Jun 2016 07:39:59 +0000 (13:09 +0530)]
net: marvell: Add separate config ANEG function for Marvell 88E1111
Marvell 88E1111 currently uses the generic marvell config ANEG function.
This function has a sequence accessing Page 5 and Register 31,
both of which are not defined or reserved for this PHY.
Hence this patch adds a new config ANEG function for Marvell 88E1111
without these erroneous accesses.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Michael Gill [Thu, 23 Jun 2016 16:55:24 +0000 (09:55 -0700)]
staging: apf: Fix crash in APF DMA associated with IP change
The SG-DMA IP changed slightly, causing the APF DMA to occasionally
fail to correctly write 64-bit addresses to IP registers. This
change corrects that problem.
Signed-off-by: Michael Gill <gill@xilinx.com> Tested-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Fri, 17 Jun 2016 23:37:09 +0000 (16:37 -0700)]
phy: zynqmp: Reset the de-emphasis and swing control for DP
When the PHY lane is initialized for DP, the de-emphasis / swing control
should be reset in order to override the values from DP with values
programmed in the register.
Hyun Kwon [Fri, 17 Jun 2016 23:37:07 +0000 (16:37 -0700)]
drm: xilinx: dp: Reduce the bit rate if the link training fails
Per DP 1.2 spec, when the linke training fails and there's
more low link rate available to try, it needs to retry
the link training with lower link rate. Since the link rate
depends on the current mode, move the training sequence to
mode set, and update other configuration such as init wait value
accordingly.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Fri, 17 Jun 2016 23:37:06 +0000 (16:37 -0700)]
drm: xilinx: dp: Set maximum swing / preemphsis level to 2 for ZynqMP
The DP spec defines that the level 3 is optional to support for both
voltage swing and preemphasis. Thus, set the maximum voltage swing
and preemphasis level to 2 for ZynqMP DP subsystem.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Brijesh Singh [Wed, 28 Oct 2015 16:13:49 +0000 (11:13 -0500)]
EDAC: Add ARM64 EDAC
Add support for Cortex A57 and A53 EDAC driver.
Note: This is v4 from mainline which hasn't been merged to mainline
because of some problems regarding CPU clusters, ACPI, etc.
But for our usecase this should be fine.
Iban Rodriguez [Mon, 13 Jun 2016 10:53:39 +0000 (12:53 +0200)]
gpio: xilinx: Always use own xlate function
General kernel function of_gpio_simple_xlate is not valid for
dual gpio devices as it always returns the gpio in the first
channel. Use own xlate function always and not only when gpio irq
is present.
Signed-off-by: Iban Rodriguez <irodriguez@cemitec.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller.
Add a reset controller driver for Xilinx Zynq UltraScale+ MPSoC.
The zynqmp reset-controller has the ability to reset lines
connected to different blocks and peripheral in the Soc.
Signed-off-by: Nava kishore Manne <navam@xilinx.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Wed, 8 Jun 2016 22:15:34 +0000 (15:15 -0700)]
staging: apf: Adding try-wait support for APF DMA
This patch adds a non-blocking poll of the scatter-gather APF DMA
done state. This is used to implement 'try-wait', which is a new
feature introduced into user space runtimes for SDSoC.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Preetesh Parekh [Fri, 3 Jun 2016 02:21:46 +0000 (19:21 -0700)]
drm: xilinx: crtc: Add crtc set config helper
The goal is to be able to synchronize resolution changes between the
drm device and emulated fbdev device if both devices are used by an
application e.g. in Qt we use both graphics and video layer whereas
the former is controlled by fbdev and the latter by drm. This patch
propagates resolution changes from the drm device to fbdev. Before
setting the new mode, a copy of the old mode is saved locally and
restored upon last close.
work in progres:
If hot-plug events happen while the application is running, the mode
pre-application start will be restored instead of the mode set by the
last hot-plug event. For example if we switch monitors from 1080p to
4k while the application is running, last close will restore the
fbconsole to 1080p on the 4k monitor. The framebuffer for the fbdev
emulation is allocated when the driver is initialized, thus hotplug
between monitors with different resolutions
(ex, 2560x1440->1920x1080) wouldn’t work correctly as of now.
Michael Gill [Fri, 3 Jun 2016 01:21:20 +0000 (18:21 -0700)]
staging: apf: Fixed DMA-BUF used of buffers spanning partial pages
The DRM infrastructure when using the xilinx driver has a
potential to return a buffer mapped to a memory region spanning a
partial page, such as in the case of a 1920x1080 resolution
buffer. When this happens, the scatterlist returned from the DRM
API describes a region rounded up to a whole page. This patch
trims the returned scatterlist, thus making it usable by a DMA.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 3 Jun 2016 01:21:19 +0000 (18:21 -0700)]
staging: apf: Fix length for non-aligned(4K) DMA-BUF SG
Iterate through DMA-BUF SG list and set length equal to
buffer size.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch fixes this issue in the driver
--> By updating the number of arguments in the flow handler to one.
--> Use irq_desc_get_chip instead of irq_get_chip
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 20 May 2016 19:40:21 +0000 (12:40 -0700)]
staging: apf: Fixed buffer over run related to page pinning
The data structure used for storing pinned user space page
structures was a constant size. Now it is adjustable
to accommodate large transfers from malloc allocated buffers
Signed-off-by: Michael Gill <gill@xilinx.com>
Tested-by : Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 20 May 2016 19:40:05 +0000 (12:40 -0700)]
staging: apf: Enable MPSoC SG-DMA and removed clock control
This patch enables preliminary scatter-gather support for the
apf DMA driver. This extends only to memory allocated by a call
to sds_alloc, and dma_buf shared buffers. Zynq support is
unchanged. Additionally, control over clocks has been removed
due to clocks being correctly configured during petalinux
boot. There is no impact of this on a user.
Signed-off-by: Michael Gill <gill@xilinx.com>
Tested-by : Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: xilinx: Remove bitbang and register with spi core
This patch removes the bitbang layer registration.
it directly register with spi core using spi_register_master and uses
the call backs provided by spi_master struct.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>