zynq/microblaze: pcie: Modified to support PCIe node ranges property

There is a change in ranges property of PCIe node in device-tree, for which the driver needs support. This commit fix this.

Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/Documentation/devicetree/bindings/pci/xilinx-axipcie.txt b/Documentation/devicetree/bindings/pci/xilinx-axipcie.txt
index e87725dbee863e3bdca95b1d62c8cbd11660f85a..edefc0c583fa4dc0eaab44bce7dbce4ce31e0d10 100644 (file)
--- a/Documentation/devicetree/bindings/pci/xilinx-axipcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-axipcie.txt
@@ -5,6 +5,8 @@ Required properties:
        reg: Should contain AXI PCIe registers location and length.
        interrupts: Should contain AXI PCIe interrupts.
        ranges: These are the parameters for each PCIe bar implemented within the IP
+       The ranges property is <<child address> <parent address> <size>>.
+       The parent address #address-cells is taken from the parent node.
        xlnx, include-rc: Root Port (=1) or End Point(=0)
        xlnx,axibar2pciebar-0: Translates address from AXI to PCIe
        xlnx,pciebar2axibar-0: Translates address from PCIe to AXI
@@ -12,12 +14,18 @@ Required properties:
 Example:
 ++++++++
 
-       pci_express: axi-pcie@50000000 {
-               compatible = "xlnx,axi-pcie-1.05.a";
-               interrupts = < 0 52 4 >;
-               ranges = < 0x00000002 0x00000000 0x60000000 0x60000000 0x00000000 0x00000000 0x10000000 >;
-               reg = < 0x50000000 0x10000000 >;
-               xlnx,include-rc = <0x1>;
-               xlnx,axibar2pciebar-0 = <0x60000000>;
-               xlnx,pciebar2axibar-0 = <0x0>;
-       };
+       ps7_axi_interconnect_0: axi@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               pci_express: axi-pcie@50000000 {
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       compatible = "xlnx,axi-pcie-1.05.a";
+                       interrupts = < 0 52 4 >;
+                       ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
+                       reg = < 0x50000000 0x10000000 >;
+                       xlnx,include-rc = <0x1>;
+                       xlnx,axibar2pciebar-0 = <0x60000000>;
+                       xlnx,pciebar2axibar-0 = <0x0>;
+               };
+       };

diff --git a/arch/arm/mach-zynq/xaxipcie.c b/arch/arm/mach-zynq/xaxipcie.c
index baf14448a8c7ab555304623cec4efc4a85f3a46c..447a613016a25849defc1ff45fe1bece34bf9d0e 100644 (file)
--- a/arch/arm/mach-zynq/xaxipcie.c
+++ b/arch/arm/mach-zynq/xaxipcie.c
@@ -372,7 +372,7 @@ void __devinit xaxi_pcie_set_bridge_resource(struct xaxi_pcie_port *port)
        u32 val = 0;
 
        while ((rlen -= np * 4) >= 0) {
-               pci_space = ranges[0];
+               pci_space = be32_to_cpup(ranges);
                pci_addr = of_read_number(ranges + 1, 2);
                size = of_read_number(ranges + port->pna + 3, 2);
 
@@ -503,7 +503,7 @@ void __devinit xaxi_pcie_process_bridge_OF_ranges(
        pr_debug("Parsing ranges property...\n");
        while ((rlen -= np * 4) >= 0) {
                /* Read next ranges element */
-               pci_space = ranges[0];
+               pci_space = be32_to_cpup(ranges);
                pci_addr = of_read_number(ranges + 1, 2);
                cpu_addr = of_translate_address(node, ranges + 3);
                size = of_read_number(ranges + pna + 3, 2);
@@ -525,7 +525,7 @@ void __devinit xaxi_pcie_process_bridge_OF_ranges(
                /* Now consume following elements while they are contiguous */
                for (; rlen >= np * sizeof(u32);
                        ranges += np, rlen -= np * 4) {
-                       if (ranges[0] != pci_space)
+                       if (be32_to_cpup(ranges) != pci_space)
                                break;
                        pci_next = of_read_number(ranges + 1, 2);
                        cpu_next = of_translate_address(node, ranges + 3);
@@ -983,11 +983,7 @@ int __devinit xaxi_pcie_get_of_config(struct device_node *node,
                return -ENODEV;
 
        /* The address cells of PCIe node */
-       value = (u32 *) of_get_property(node, "#address-cells", NULL);
-       if (value)
-               info->address_cells = be32_to_cpup(value);
-       else
-               return -ENODEV;
+       info->address_cells = of_n_addr_cells(node);
 
        /* Get ranges property */
        value = (u32 *) of_get_property(node, "ranges", &rlen);

diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index bc569478e6f6eaeb42f9cfeaa6b3f3210d691cba..52e6ab4e76934b967aa53ced8a0af2267c8d766f 100644 (file)
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -661,12 +661,8 @@ void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
 {
        const u32 *ranges;
        int rlen;
-#ifdef CONFIG_XILINX_AXIPCIE
-       /* The address cells of PCIe node */
-       int pna = be32_to_cpup(of_get_property(dev, "#address-cells", NULL));
-#else
+       /* The address cells of PCIe parent node */
        int pna = of_n_addr_cells(dev);
-#endif
        int np = pna + 5;
        int memno = 0, isa_hole = -1;
        u32 pci_space;
@@ -686,7 +682,7 @@ void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
        pr_debug("Parsing ranges property...\n");
        while ((rlen -= np * 4) >= 0) {
                /* Read next ranges element */
-               pci_space = ranges[0];
+               pci_space = be32_to_cpup(ranges);
                pci_addr = of_read_number(ranges + 1, 2);
                cpu_addr = of_translate_address(dev, ranges + 3);
                size = of_read_number(ranges + pna + 3, 2);
@@ -708,7 +704,7 @@ void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
                /* Now consume following elements while they are contiguous */
                for (; rlen >= np * sizeof(u32);
                     ranges += np, rlen -= np * 4) {
-                       if (ranges[0] != pci_space)
+                       if (be32_to_cpup(ranges) != pci_space)
                                break;
                        pci_next = of_read_number(ranges + 1, 2);
                        cpu_next = of_translate_address(dev, ranges + 3);

diff --git a/arch/microblaze/pci/xilinx_axipcie.c b/arch/microblaze/pci/xilinx_axipcie.c
index e5fbe7d43849f216275d5ba78824e3a0a56b4ca2..22bd466920a6027a4e33f8d39d930fcc88f261b7 100644 (file)
--- a/arch/microblaze/pci/xilinx_axipcie.c
+++ b/arch/microblaze/pci/xilinx_axipcie.c
@@ -413,9 +413,8 @@ void __devinit xilinx_set_bridge_resource(struct xilinx_axipcie_port *port)
 {
        const u32 *ranges;
        int rlen;
-       /* The address cells of PCIe node */
-       int pna = be32_to_cpup(of_get_property(port->node,
-                                       "#address-cells", NULL));
+       /* The address cells of PCIe parent node */
+       int pna = of_n_addr_cells(port->node);
        int np = pna + 5;
        u32 pci_space;
        unsigned long long pci_addr, size;
@@ -433,7 +432,7 @@ void __devinit xilinx_set_bridge_resource(struct xilinx_axipcie_port *port)
        }
 
        while ((rlen -= np * 4) >= 0) {
-               pci_space = ranges[0];
+               pci_space = be32_to_cpup(ranges);
                pci_addr = of_read_number(ranges + 1, 2);
                size = of_read_number(ranges + pna + 3, 2);