clk: zynqmp: pll: Do correct rounding for max and min requirements

The fbdiv for max value should be rounded down to make sure the rate
never goes above the max rate. On the other hand, the fbdiv for
the min should be rounded up so that the resulted rate is above
the minimum rate.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
index 342375333ff947a507e33dd83ac287beb4c139f7..d9ae8aa1091e3616d59f944c7305c6a3b5b09008 100644 (file)
--- a/drivers/clk/zynqmp/pll.c
+++ b/drivers/clk/zynqmp/pll.c
@@ -122,11 +122,11 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 
        if (pll_frac_get_mode(hw) == PLL_MODE_FRAC) {
                if (rate > PS_PLL_VCO_MAX) {
-                       fbdiv = DIV_ROUND_CLOSEST(rate, PS_PLL_VCO_MAX);
+                       fbdiv = rate / PS_PLL_VCO_MAX;
                        rate = rate / (fbdiv + 1);
                }
                if (rate < PS_PLL_VCO_MIN) {
-                       fbdiv = DIV_ROUND_CLOSEST(PS_PLL_VCO_MIN, rate);
+                       fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
                        rate = rate * fbdiv;
                }
                return rate;