spi: zynq-qspi: Wait for FIFO to be empty when switching TXD registers

When switching from TXD0 to TXD1/2/3, software has to wait for FIFO to be
empty before writing to TXD1/2/3 as per the documentation.

Although previous discussions and tests revealed that this waiting
is required only for TXD1/2/3 to TXD0 switches and not vice-verse,
design team conveyed that TXD0 to TXD1/2/3 switching can behave unpredictably
if wait is not used. Hence this change is made to comply.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
index 98e1047473ec01daa9919e911efbdde9710a31b4..ee1d6226b0239c9605b9a4ff4552d3263caae5f2 100644 (file)
--- a/drivers/spi/spi-zynq-qspi.c
+++ b/drivers/spi/spi-zynq-qspi.c
@@ -540,7 +540,7 @@ static irqreturn_t zynq_qspi_irq(int irq, void *dev_id)
                                /* There is more data to send */
                                zynq_qspi_fill_tx_fifo(xqspi,
                                                       ZYNQ_QSPI_RX_THRESHOLD);
-                       } else {
+                       } else if (intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK) {
                                int tmp;
                                tmp = xqspi->bytes_to_transfer;
                                zynq_qspi_copy_write_data(xqspi, &data,