phy: dp83867: Add support for SGMII

Add init configuration for SGMII for TI DP83867 PHY.
-> Enable SGMII and PCS settings in PHY control, CFG2 and BIST registers.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index 8ccdd531eeb0b02299d352823330407a3e84b067..506d2907d567585462149c5eed9280b6d08ec619 100644 (file)
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -28,6 +28,8 @@
 #define MII_DP83867_PHYCTRL    0x10
 #define MII_DP83867_MICR       0x12
 #define MII_DP83867_ISR                0x13
+#define MII_DP83867_CFG2       0x14
+#define MII_DP83867_BISCR      0x16
 #define DP83867_CTRL           0x1f
 
 /* Extended Registers */
@@ -59,10 +61,21 @@
 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT         14
 #define DP83867_MDI_CROSSOVER          5
 #define DP83867_MDI_CROSSOVER_AUTO     0b10
+#define DP83867_MDI_CROSSOVER_MDIX     0b01
+#define DP83867_PHYCTRL_SGMIIEN                        0x0800
+#define DP83867_PHYCTRL_RXFIFO_SHIFT   12
+#define DP83867_PHYCTRL_TXFIFO_SHIFT   14
 
 /* RGMIIDCTL bits */
 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT       4
 
+/* CFG2 bits */
+#define MII_DP83867_CFG2_SPEEDOPT_10EN         0x0040
+#define MII_DP83867_CFG2_SPEEDOPT_ENH          0x0100
+#define MII_DP83867_CFG2_SPEEDOPT_CNT          0x0800
+#define MII_DP83867_CFG2_SPEEDOPT_INTLOW       0x2000
+#define MII_DP83867_CFG2_MASK                  0x003F
+
 struct dp83867_private {
        int rx_id_delay;
        int tx_id_delay;
@@ -139,7 +152,7 @@ static int dp83867_config_init(struct phy_device *phydev)
 {
        struct dp83867_private *dp83867;
        int ret;
-       u16 val, delay;
+       u16 val, delay, cfg2;
 
        if (!phydev->priv) {
                dp83867 = devm_kzalloc(&phydev->dev, sizeof(*dp83867),
@@ -161,6 +174,27 @@ static int dp83867_config_init(struct phy_device *phydev)
                        (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
                if (ret)
                        return ret;
+       } else {
+               phy_write(phydev, MII_BMCR,
+                         (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
+
+               cfg2 = phy_read(phydev, MII_DP83867_CFG2);
+               cfg2 &= MII_DP83867_CFG2_MASK;
+               cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
+                        MII_DP83867_CFG2_SPEEDOPT_ENH |
+                        MII_DP83867_CFG2_SPEEDOPT_CNT |
+                        MII_DP83867_CFG2_SPEEDOPT_INTLOW);
+               phy_write(phydev, MII_DP83867_CFG2, cfg2);
+
+               phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
+                                      DP83867_DEVADDR, phydev->addr, 0x0);
+
+               phy_write(phydev, MII_DP83867_PHYCTRL,
+                         DP83867_PHYCTRL_SGMIIEN |
+                         (DP83867_MDI_CROSSOVER_MDIX << DP83867_MDI_CROSSOVER) |
+                         (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
+                         (dp83867->fifo_depth  << DP83867_PHYCTRL_TXFIFO_SHIFT));
+               phy_write(phydev, MII_DP83867_BISCR, 0x0);
        }
 
        if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&