zynq: clk: Move topswitch code from PM driver

This is purely clock code and should be in clock driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/mach-zynq/pm.c b/arch/arm/mach-zynq/pm.c
index 84f1a2629507a55923b0e168068b2282373eb32f..d28a3aa422fb8c4cf1168cd85aff826071233ee9 100644 (file)
--- a/arch/arm/mach-zynq/pm.c
+++ b/arch/arm/mach-zynq/pm.c
@@ -38,12 +38,10 @@
 #define DDRC_CTRL_REG1_OFFS            0x60
 #define DDRC_DRAM_PARAM_REG3_OFFS      0x20
 #define SCU_CTRL                       0
-#define SLCR_TOPSW_CLK_CTRL            0x16c
 
 #define DDRC_CLOCKSTOP_MASK    BIT(23)
 #define DDRC_SELFREFRESH_MASK  BIT(12)
 #define SCU_STBY_EN_MASK       BIT(5)
-#define TOPSW_CLK_CTRL_DIS_MASK        BIT(0)
 
 static void __iomem *ddrc_base;
 static void __iomem *ocm_base;
@@ -91,9 +89,7 @@ static int zynq_pm_suspend(unsigned long arg)
        }
 
        /* Topswitch clock stop disable */
-       reg = zynq_slcr_read(SLCR_TOPSW_CLK_CTRL);
-       reg |= TOPSW_CLK_CTRL_DIS_MASK;
-       zynq_slcr_write(reg, SLCR_TOPSW_CLK_CTRL);
+       zynq_clk_topswitch_disable();
 
        /* A9 clock gating */
        asm volatile ("mrc  p15, 0, r12, c15, c0, 0\n"
@@ -146,10 +142,8 @@ static int zynq_pm_suspend(unsigned long arg)
                kfree(ocm_swap_area);
        }
 
-       /* Topswitch clock stop disable */
-       reg = zynq_slcr_read(SLCR_TOPSW_CLK_CTRL);
-       reg &= ~TOPSW_CLK_CTRL_DIS_MASK;
-       zynq_slcr_write(reg, SLCR_TOPSW_CLK_CTRL);
+       /* Topswitch clock stop enable */
+       zynq_clk_topswitch_enable();
 
        /* SCU standby mode */
        if (zynq_scu_base) {

diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 54723beda02368bee4ddac810aaf4fc647211484..efd41e8f65483ac40853c878eb5f2b1b8c01bc84 100644 (file)
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -47,6 +47,7 @@ static void __iomem *zynq_slcr_base_priv;
 #define SLCR_CAN_MIOCLK_CTRL           (zynq_slcr_base_priv + 0x160)
 #define SLCR_DBG_CLK_CTRL              (zynq_slcr_base_priv + 0x164)
 #define SLCR_PCAP_CLK_CTRL             (zynq_slcr_base_priv + 0x168)
+#define SLCR_TOPSW_CLK_CTRL            (zynq_slcr_base_priv + 0x16c)
 #define SLCR_FPGA0_CLK_CTRL            (zynq_slcr_base_priv + 0x170)
 #define SLCR_621_TRUE                  (zynq_slcr_base_priv + 0x1c4)
 #define SLCR_SWDT_CLK_SEL              (zynq_slcr_base_priv + 0x304)
@@ -106,6 +107,8 @@ unsigned int zynq_clk_suspended;
 static struct clk *armpll_save_parent;
 static struct clk *iopll_save_parent;
 
+#define TOPSW_CLK_CTRL_DIS_MASK        BIT(0)
+
 int zynq_clk_suspend_early(void)
 {
        int ret;
@@ -133,6 +136,24 @@ void zynq_clk_resume_late(void)
 
        zynq_clk_suspended = 0;
 }
+
+void zynq_clk_topswitch_enable(void)
+{
+       u32 reg;
+
+       reg = readl(SLCR_TOPSW_CLK_CTRL);
+       reg &= ~TOPSW_CLK_CTRL_DIS_MASK;
+       writel(reg, SLCR_TOPSW_CLK_CTRL);
+}
+
+void zynq_clk_topswitch_disable(void)
+{
+       u32 reg;
+
+       reg = readl(SLCR_TOPSW_CLK_CTRL);
+       reg |= TOPSW_CLK_CTRL_DIS_MASK;
+       writel(reg, SLCR_TOPSW_CLK_CTRL);
+}
 #endif
 
 static void __init zynq_clk_register_fclk(enum zynq_clk fclk,

diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h
index 4003fb46227d9c000eb14f63b9ddc36e0a798f1f..96624153c72c4a745a17a73b2a1d3fad756304b7 100644 (file)
--- a/include/linux/clk/zynq.h
+++ b/include/linux/clk/zynq.h
@@ -26,6 +26,8 @@ extern unsigned int zynq_clk_suspended;
 
 int zynq_clk_suspend_early(void);
 void zynq_clk_resume_late(void);
+void zynq_clk_topswitch_enable(void);
+void zynq_clk_topswitch_disable(void);
 void zynq_clock_init(void __iomem *slcr);
 
 struct clk *clk_register_zynq_pll(const char *name, const char *parent,