*-----------------------------------------------------------------------------
*/
#define ROE_FRAMER_V1_0_CFG_BASE_ADDR 0x0 /* 0 */
-#define ROE_FRAMER_V1_0_FRAM_BASE_ADDR 0x8192 /* 8192 */
-#define ROE_FRAMER_V1_0_FRAM_DRP_BASE_ADDR 0x16384 /* 16384 */
-#define ROE_FRAMER_V1_0_DEFM_BASE_ADDR 0x24576 /* 24576 */
-#define ROE_FRAMER_V1_0_DEFM_DRP_BASE_ADDR 0x32768 /* 32768 */
-#define ROE_FRAMER_V1_0_ETH_BASE_ADDR 0x40960 /* 40960 */
-#define ROE_FRAMER_V1_0_STATS_BASE_ADDR 0x49152 /* 49152 */
+#define ROE_FRAMER_V1_0_FRAM_BASE_ADDR 0x2000 /* 8192 */
+#define ROE_FRAMER_V1_0_FRAM_DRP_BASE_ADDR 0x4000 /* 16384 */
+#define ROE_FRAMER_V1_0_DEFM_BASE_ADDR 0x6000 /* 24576 */
+#define ROE_FRAMER_V1_0_DEFM_DRP_BASE_ADDR 0x8000 /* 32768 */
+#define ROE_FRAMER_V1_0_ETH_BASE_ADDR 0xa000 /* 40960 */
+#define ROE_FRAMER_V1_0_STATS_BASE_ADDR 0xc000 /* 49152 */
/*-----------------------------------------------------------------------------
* C Header bank register definitions for bank roe_framer_v1_0_cfg
*/
/* Type = roInt */
#define CFG_MAJOR_REVISION_ADDR 0x0 /* 0 */
-#define CFG_MAJOR_REVISION_MASK 0x4278190080 /* 4278190080 */
-#define CFG_MAJOR_REVISION_OFFSET 0x24 /* 24 */
+#define CFG_MAJOR_REVISION_MASK 0xff000000 /* 4278190080 */
+#define CFG_MAJOR_REVISION_OFFSET 0x18 /* 24 */
#define CFG_MAJOR_REVISION_WIDTH 0x8 /* 8 */
#define CFG_MAJOR_REVISION_DEFAULT 0x1 /* 1 */
/* Type = roInt */
#define CFG_MINOR_REVISION_ADDR 0x0 /* 0 */
-#define CFG_MINOR_REVISION_MASK 0x16711680 /* 16711680 */
-#define CFG_MINOR_REVISION_OFFSET 0x16 /* 16 */
+#define CFG_MINOR_REVISION_MASK 0xff0000 /* 16711680 */
+#define CFG_MINOR_REVISION_OFFSET 0x10 /* 16 */
#define CFG_MINOR_REVISION_WIDTH 0x8 /* 8 */
#define CFG_MINOR_REVISION_DEFAULT 0x0 /* 0 */
/* Type = roInt */
#define CFG_VERSION_REVISION_ADDR 0x0 /* 0 */
-#define CFG_VERSION_REVISION_MASK 0x65280 /* 65280 */
+#define CFG_VERSION_REVISION_MASK 0xff00 /* 65280 */
#define CFG_VERSION_REVISION_OFFSET 0x8 /* 8 */
#define CFG_VERSION_REVISION_WIDTH 0x8 /* 8 */
#define CFG_VERSION_REVISION_DEFAULT 0x0 /* 0 */
/* Type = roInt */
#define CFG_INTERNAL_REVISION_ADDR 0x4 /* 4 */
-#define CFG_INTERNAL_REVISION_MASK 0x4294967295 /* 4294967295 */
+#define CFG_INTERNAL_REVISION_MASK 0xffffffff /* 4294967295 */
#define CFG_INTERNAL_REVISION_OFFSET 0x0 /* 0 */
-#define CFG_INTERNAL_REVISION_WIDTH 0x32 /* 32 */
-#define CFG_INTERNAL_REVISION_DEFAULT 0x305419896 /* 305419896 */
+#define CFG_INTERNAL_REVISION_WIDTH 0x20 /* 32 */
+#define CFG_INTERNAL_REVISION_DEFAULT 0x12345678 /* 305419896 */
/* Type = rw */
#define CFG_TIMEOUT_VALUE_ADDR 0x8 /* 8 */
-#define CFG_TIMEOUT_VALUE_MASK 0x4095 /* 4095 */
+#define CFG_TIMEOUT_VALUE_MASK 0xfff /* 4095 */
#define CFG_TIMEOUT_VALUE_OFFSET 0x0 /* 0 */
-#define CFG_TIMEOUT_VALUE_WIDTH 0x12 /* 12 */
-#define CFG_TIMEOUT_VALUE_DEFAULT 0x128 /* 128 */
+#define CFG_TIMEOUT_VALUE_WIDTH 0xc /* 12 */
+#define CFG_TIMEOUT_VALUE_DEFAULT 0x80 /* 128 */
/* Type = rw */
-#define CFG_USER_RW_OUT_ADDR 0x12 /* 12 */
-#define CFG_USER_RW_OUT_MASK 0x255 /* 255 */
+#define CFG_USER_RW_OUT_ADDR 0xc /* 12 */
+#define CFG_USER_RW_OUT_MASK 0xff /* 255 */
#define CFG_USER_RW_OUT_OFFSET 0x0 /* 0 */
#define CFG_USER_RW_OUT_WIDTH 0x8 /* 8 */
#define CFG_USER_RW_OUT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define CFG_USER_RO_IN_ADDR 0x12 /* 12 */
-#define CFG_USER_RO_IN_MASK 0x16711680 /* 16711680 */
-#define CFG_USER_RO_IN_OFFSET 0x16 /* 16 */
+#define CFG_USER_RO_IN_ADDR 0xc /* 12 */
+#define CFG_USER_RO_IN_MASK 0xff0000 /* 16711680 */
+#define CFG_USER_RO_IN_OFFSET 0x10 /* 16 */
#define CFG_USER_RO_IN_WIDTH 0x8 /* 8 */
#define CFG_USER_RO_IN_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define CFG_MASTER_INT_ENABLE_ADDR 0x16 /* 16 */
+#define CFG_MASTER_INT_ENABLE_ADDR 0x10 /* 16 */
#define CFG_MASTER_INT_ENABLE_MASK 0x1 /* 1 */
#define CFG_MASTER_INT_ENABLE_OFFSET 0x0 /* 0 */
#define CFG_MASTER_INT_ENABLE_WIDTH 0x1 /* 1 */
#define CFG_MASTER_INT_ENABLE_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define CFG_AXI_TIMEOUT_ENABLE_ADDR 0x20 /* 20 */
-#define CFG_AXI_TIMEOUT_ENABLE_MASK 0x2147483648 /* 2147483648 */
-#define CFG_AXI_TIMEOUT_ENABLE_OFFSET 0x31 /* 31 */
+#define CFG_AXI_TIMEOUT_ENABLE_ADDR 0x14 /* 20 */
+#define CFG_AXI_TIMEOUT_ENABLE_MASK 0x80000000 /* 2147483648 */
+#define CFG_AXI_TIMEOUT_ENABLE_OFFSET 0x1f /* 31 */
#define CFG_AXI_TIMEOUT_ENABLE_WIDTH 0x1 /* 1 */
#define CFG_AXI_TIMEOUT_ENABLE_DEFAULT 0x1 /* 1 */
/* Type = roSig */
-#define CFG_AXI_TIMEOUT_STATUS_ADDR 0x24 /* 24 */
-#define CFG_AXI_TIMEOUT_STATUS_MASK 0x2147483648 /* 2147483648 */
-#define CFG_AXI_TIMEOUT_STATUS_OFFSET 0x31 /* 31 */
+#define CFG_AXI_TIMEOUT_STATUS_ADDR 0x18 /* 24 */
+#define CFG_AXI_TIMEOUT_STATUS_MASK 0x80000000 /* 2147483648 */
+#define CFG_AXI_TIMEOUT_STATUS_OFFSET 0x1f /* 31 */
#define CFG_AXI_TIMEOUT_STATUS_WIDTH 0x1 /* 1 */
#define CFG_AXI_TIMEOUT_STATUS_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define CFG_CONFIG_NO_OF_FRAM_ANTS_ADDR 0x32 /* 32 */
-#define CFG_CONFIG_NO_OF_FRAM_ANTS_MASK 0x65535 /* 65535 */
+#define CFG_CONFIG_NO_OF_FRAM_ANTS_ADDR 0x20 /* 32 */
+#define CFG_CONFIG_NO_OF_FRAM_ANTS_MASK 0xffff /* 65535 */
#define CFG_CONFIG_NO_OF_FRAM_ANTS_OFFSET 0x0 /* 0 */
-#define CFG_CONFIG_NO_OF_FRAM_ANTS_WIDTH 0x16 /* 16 */
+#define CFG_CONFIG_NO_OF_FRAM_ANTS_WIDTH 0x10 /* 16 */
#define CFG_CONFIG_NO_OF_FRAM_ANTS_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define CFG_CONFIG_NO_OF_DEFM_ANTS_ADDR 0x32 /* 32 */
-#define CFG_CONFIG_NO_OF_DEFM_ANTS_MASK 0x4294901760 /* 4294901760 */
-#define CFG_CONFIG_NO_OF_DEFM_ANTS_OFFSET 0x16 /* 16 */
-#define CFG_CONFIG_NO_OF_DEFM_ANTS_WIDTH 0x16 /* 16 */
+#define CFG_CONFIG_NO_OF_DEFM_ANTS_ADDR 0x20 /* 32 */
+#define CFG_CONFIG_NO_OF_DEFM_ANTS_MASK 0xffff0000 /* 4294901760 */
+#define CFG_CONFIG_NO_OF_DEFM_ANTS_OFFSET 0x10 /* 16 */
+#define CFG_CONFIG_NO_OF_DEFM_ANTS_WIDTH 0x10 /* 16 */
#define CFG_CONFIG_NO_OF_DEFM_ANTS_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define CFG_CONFIG_NO_OF_ETH_PORTS_ADDR 0x36 /* 36 */
-#define CFG_CONFIG_NO_OF_ETH_PORTS_MASK 0x1023 /* 1023 */
+#define CFG_CONFIG_NO_OF_ETH_PORTS_ADDR 0x24 /* 36 */
+#define CFG_CONFIG_NO_OF_ETH_PORTS_MASK 0x3ff /* 1023 */
#define CFG_CONFIG_NO_OF_ETH_PORTS_OFFSET 0x0 /* 0 */
-#define CFG_CONFIG_NO_OF_ETH_PORTS_WIDTH 0x10 /* 10 */
+#define CFG_CONFIG_NO_OF_ETH_PORTS_WIDTH 0xa /* 10 */
#define CFG_CONFIG_NO_OF_ETH_PORTS_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define CFG_CONFIG_ETH_SPEED_ADDR 0x36 /* 36 */
-#define CFG_CONFIG_ETH_SPEED_MASK 0x67043328 /* 67043328 */
-#define CFG_CONFIG_ETH_SPEED_OFFSET 0x16 /* 16 */
-#define CFG_CONFIG_ETH_SPEED_WIDTH 0x10 /* 10 */
+#define CFG_CONFIG_ETH_SPEED_ADDR 0x24 /* 36 */
+#define CFG_CONFIG_ETH_SPEED_MASK 0x3ff0000 /* 67043328 */
+#define CFG_CONFIG_ETH_SPEED_OFFSET 0x10 /* 16 */
+#define CFG_CONFIG_ETH_SPEED_WIDTH 0xa /* 10 */
#define CFG_CONFIG_ETH_SPEED_DEFAULT 0x0 /* 0 */
/*-----------------------------------------------------------------------------
* C Header bank register definitions for bank roe_framer_v1_0_fram
* with prefix fram_ @ address 0x2000
- *-----------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
*/
/* Type = rwpdef */
-#define FRAM_RESTART_ADDR 0x8192 /* 8192 */
+#define FRAM_RESTART_ADDR 0x2000 /* 8192 */
#define FRAM_RESTART_MASK 0x1 /* 1 */
#define FRAM_RESTART_OFFSET 0x0 /* 0 */
#define FRAM_RESTART_WIDTH 0x1 /* 1 */
#define FRAM_RESTART_DEFAULT 0x1 /* 1 */
/* Type = roSig */
-#define FRAM_READY_ADDR 0x8192 /* 8192 */
+#define FRAM_READY_ADDR 0x2000 /* 8192 */
#define FRAM_READY_MASK 0x2 /* 2 */
#define FRAM_READY_OFFSET 0x1 /* 1 */
#define FRAM_READY_WIDTH 0x1 /* 1 */
#define FRAM_READY_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define FRAM_AUTO_RESTART_CNT_ADDR 0x8196 /* 8196 */
-#define FRAM_AUTO_RESTART_CNT_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_AUTO_RESTART_CNT_ADDR 0x2004 /* 8196 */
+#define FRAM_AUTO_RESTART_CNT_MASK 0xffffffff /* 4294967295 */
#define FRAM_AUTO_RESTART_CNT_OFFSET 0x0 /* 0 */
-#define FRAM_AUTO_RESTART_CNT_WIDTH 0x32 /* 32 */
+#define FRAM_AUTO_RESTART_CNT_WIDTH 0x20 /* 32 */
#define FRAM_AUTO_RESTART_CNT_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define FRAM_SN_DATA_LOW_CNT_MIN_ADDR 0x8224 /* 8224 */
-#define FRAM_SN_DATA_LOW_CNT_MIN_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_DATA_LOW_CNT_MIN_ADDR 0x2020 /* 8224 */
+#define FRAM_SN_DATA_LOW_CNT_MIN_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_DATA_LOW_CNT_MIN_OFFSET 0x0 /* 0 */
-#define FRAM_SN_DATA_LOW_CNT_MIN_WIDTH 0x32 /* 32 */
+#define FRAM_SN_DATA_LOW_CNT_MIN_WIDTH 0x20 /* 32 */
#define FRAM_SN_DATA_LOW_CNT_MIN_DEFAULT 0x1 /* 1 */
/* Type = rw */
-#define FRAM_SN_DATA_LOW_CNT_MAX_ADDR 0x8228 /* 8228 */
-#define FRAM_SN_DATA_LOW_CNT_MAX_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_DATA_LOW_CNT_MAX_ADDR 0x2024 /* 8228 */
+#define FRAM_SN_DATA_LOW_CNT_MAX_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_DATA_LOW_CNT_MAX_OFFSET 0x0 /* 0 */
-#define FRAM_SN_DATA_LOW_CNT_MAX_WIDTH 0x32 /* 32 */
-#define FRAM_SN_DATA_LOW_CNT_MAX_DEFAULT 0x120 /* 120 */
+#define FRAM_SN_DATA_LOW_CNT_MAX_WIDTH 0x20 /* 32 */
+#define FRAM_SN_DATA_LOW_CNT_MAX_DEFAULT 0x78 /* 120 */
/* Type = rw */
-#define FRAM_SN_DATA_LOW_CNT_INITVAL_ADDR 0x8232 /* 8232 */
-#define FRAM_SN_DATA_LOW_CNT_INITVAL_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_DATA_LOW_CNT_INITVAL_ADDR 0x2028 /* 8232 */
+#define FRAM_SN_DATA_LOW_CNT_INITVAL_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_DATA_LOW_CNT_INITVAL_OFFSET 0x0 /* 0 */
-#define FRAM_SN_DATA_LOW_CNT_INITVAL_WIDTH 0x32 /* 32 */
-#define FRAM_SN_DATA_LOW_CNT_INITVAL_DEFAULT 0x117 /* 117 */
+#define FRAM_SN_DATA_LOW_CNT_INITVAL_WIDTH 0x20 /* 32 */
+#define FRAM_SN_DATA_LOW_CNT_INITVAL_DEFAULT 0x75 /* 117 */
/* Type = rw */
-#define FRAM_SN_DATA_LOW_CNT_INCVAL_ADDR 0x8236 /* 8236 */
-#define FRAM_SN_DATA_LOW_CNT_INCVAL_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_DATA_LOW_CNT_INCVAL_ADDR 0x202c /* 8236 */
+#define FRAM_SN_DATA_LOW_CNT_INCVAL_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_DATA_LOW_CNT_INCVAL_OFFSET 0x0 /* 0 */
-#define FRAM_SN_DATA_LOW_CNT_INCVAL_WIDTH 0x32 /* 32 */
+#define FRAM_SN_DATA_LOW_CNT_INCVAL_WIDTH 0x20 /* 32 */
#define FRAM_SN_DATA_LOW_CNT_INCVAL_DEFAULT 0x1 /* 1 */
/* Type = rw */
-#define FRAM_SN_DATA_HIGH_CNT_MIN_ADDR 0x8240 /* 8240 */
-#define FRAM_SN_DATA_HIGH_CNT_MIN_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_DATA_HIGH_CNT_MIN_ADDR 0x2030 /* 8240 */
+#define FRAM_SN_DATA_HIGH_CNT_MIN_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_DATA_HIGH_CNT_MIN_OFFSET 0x0 /* 0 */
-#define FRAM_SN_DATA_HIGH_CNT_MIN_WIDTH 0x32 /* 32 */
+#define FRAM_SN_DATA_HIGH_CNT_MIN_WIDTH 0x20 /* 32 */
#define FRAM_SN_DATA_HIGH_CNT_MIN_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define FRAM_SN_DATA_HIGH_CNT_MAX_ADDR 0x8244 /* 8244 */
-#define FRAM_SN_DATA_HIGH_CNT_MAX_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_DATA_HIGH_CNT_MAX_ADDR 0x2034 /* 8244 */
+#define FRAM_SN_DATA_HIGH_CNT_MAX_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_DATA_HIGH_CNT_MAX_OFFSET 0x0 /* 0 */
-#define FRAM_SN_DATA_HIGH_CNT_MAX_WIDTH 0x32 /* 32 */
-#define FRAM_SN_DATA_HIGH_CNT_MAX_DEFAULT 0x79 /* 79 */
+#define FRAM_SN_DATA_HIGH_CNT_MAX_WIDTH 0x20 /* 32 */
+#define FRAM_SN_DATA_HIGH_CNT_MAX_DEFAULT 0x4f /* 79 */
/* Type = rw */
-#define FRAM_SN_DATA_HIGH_CNT_INITVAL_ADDR 0x8248 /* 8248 */
-#define FRAM_SN_DATA_HIGH_CNT_INITVAL_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_DATA_HIGH_CNT_INITVAL_ADDR 0x2038 /* 8248 */
+#define FRAM_SN_DATA_HIGH_CNT_INITVAL_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_DATA_HIGH_CNT_INITVAL_OFFSET 0x0 /* 0 */
-#define FRAM_SN_DATA_HIGH_CNT_INITVAL_WIDTH 0x32 /* 32 */
-#define FRAM_SN_DATA_HIGH_CNT_INITVAL_DEFAULT 0x79 /* 79 */
+#define FRAM_SN_DATA_HIGH_CNT_INITVAL_WIDTH 0x20 /* 32 */
+#define FRAM_SN_DATA_HIGH_CNT_INITVAL_DEFAULT 0x4f /* 79 */
/* Type = rw */
-#define FRAM_SN_DATA_HIGH_CNT_INCVAL_ADDR 0x8252 /* 8252 */
-#define FRAM_SN_DATA_HIGH_CNT_INCVAL_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_DATA_HIGH_CNT_INCVAL_ADDR 0x203c /* 8252 */
+#define FRAM_SN_DATA_HIGH_CNT_INCVAL_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_DATA_HIGH_CNT_INCVAL_OFFSET 0x0 /* 0 */
-#define FRAM_SN_DATA_HIGH_CNT_INCVAL_WIDTH 0x32 /* 32 */
+#define FRAM_SN_DATA_HIGH_CNT_INCVAL_WIDTH 0x20 /* 32 */
#define FRAM_SN_DATA_HIGH_CNT_INCVAL_DEFAULT 0x1 /* 1 */
/* Type = rw */
-#define FRAM_SN_CTRL_LOW_CNT_MIN_ADDR 0x8272 /* 8272 */
-#define FRAM_SN_CTRL_LOW_CNT_MIN_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_CTRL_LOW_CNT_MIN_ADDR 0x2050 /* 8272 */
+#define FRAM_SN_CTRL_LOW_CNT_MIN_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_CTRL_LOW_CNT_MIN_OFFSET 0x0 /* 0 */
-#define FRAM_SN_CTRL_LOW_CNT_MIN_WIDTH 0x32 /* 32 */
+#define FRAM_SN_CTRL_LOW_CNT_MIN_WIDTH 0x20 /* 32 */
#define FRAM_SN_CTRL_LOW_CNT_MIN_DEFAULT 0x1 /* 1 */
/* Type = rw */
-#define FRAM_SN_CTRL_LOW_CNT_MAX_ADDR 0x8276 /* 8276 */
-#define FRAM_SN_CTRL_LOW_CNT_MAX_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_CTRL_LOW_CNT_MAX_ADDR 0x2054 /* 8276 */
+#define FRAM_SN_CTRL_LOW_CNT_MAX_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_CTRL_LOW_CNT_MAX_OFFSET 0x0 /* 0 */
-#define FRAM_SN_CTRL_LOW_CNT_MAX_WIDTH 0x32 /* 32 */
-#define FRAM_SN_CTRL_LOW_CNT_MAX_DEFAULT 0x120 /* 120 */
+#define FRAM_SN_CTRL_LOW_CNT_MAX_WIDTH 0x20 /* 32 */
+#define FRAM_SN_CTRL_LOW_CNT_MAX_DEFAULT 0x78 /* 120 */
/* Type = rw */
-#define FRAM_SN_CTRL_LOW_CNT_INITVAL_ADDR 0x8280 /* 8280 */
-#define FRAM_SN_CTRL_LOW_CNT_INITVAL_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_CTRL_LOW_CNT_INITVAL_ADDR 0x2058 /* 8280 */
+#define FRAM_SN_CTRL_LOW_CNT_INITVAL_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_CTRL_LOW_CNT_INITVAL_OFFSET 0x0 /* 0 */
-#define FRAM_SN_CTRL_LOW_CNT_INITVAL_WIDTH 0x32 /* 32 */
-#define FRAM_SN_CTRL_LOW_CNT_INITVAL_DEFAULT 0x117 /* 117 */
+#define FRAM_SN_CTRL_LOW_CNT_INITVAL_WIDTH 0x20 /* 32 */
+#define FRAM_SN_CTRL_LOW_CNT_INITVAL_DEFAULT 0x75 /* 117 */
/* Type = rw */
-#define FRAM_SN_CTRL_LOW_CNT_INCVAL_ADDR 0x8284 /* 8284 */
-#define FRAM_SN_CTRL_LOW_CNT_INCVAL_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_CTRL_LOW_CNT_INCVAL_ADDR 0x205c /* 8284 */
+#define FRAM_SN_CTRL_LOW_CNT_INCVAL_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_CTRL_LOW_CNT_INCVAL_OFFSET 0x0 /* 0 */
-#define FRAM_SN_CTRL_LOW_CNT_INCVAL_WIDTH 0x32 /* 32 */
+#define FRAM_SN_CTRL_LOW_CNT_INCVAL_WIDTH 0x20 /* 32 */
#define FRAM_SN_CTRL_LOW_CNT_INCVAL_DEFAULT 0x1 /* 1 */
/* Type = rw */
-#define FRAM_SN_CTRL_HIGH_CNT_MIN_ADDR 0x8288 /* 8288 */
-#define FRAM_SN_CTRL_HIGH_CNT_MIN_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_CTRL_HIGH_CNT_MIN_ADDR 0x2060 /* 8288 */
+#define FRAM_SN_CTRL_HIGH_CNT_MIN_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_CTRL_HIGH_CNT_MIN_OFFSET 0x0 /* 0 */
-#define FRAM_SN_CTRL_HIGH_CNT_MIN_WIDTH 0x32 /* 32 */
+#define FRAM_SN_CTRL_HIGH_CNT_MIN_WIDTH 0x20 /* 32 */
#define FRAM_SN_CTRL_HIGH_CNT_MIN_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define FRAM_SN_CTRL_HIGH_CNT_MAX_ADDR 0x8292 /* 8292 */
-#define FRAM_SN_CTRL_HIGH_CNT_MAX_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_CTRL_HIGH_CNT_MAX_ADDR 0x2064 /* 8292 */
+#define FRAM_SN_CTRL_HIGH_CNT_MAX_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_CTRL_HIGH_CNT_MAX_OFFSET 0x0 /* 0 */
-#define FRAM_SN_CTRL_HIGH_CNT_MAX_WIDTH 0x32 /* 32 */
-#define FRAM_SN_CTRL_HIGH_CNT_MAX_DEFAULT 0x79 /* 79 */
+#define FRAM_SN_CTRL_HIGH_CNT_MAX_WIDTH 0x20 /* 32 */
+#define FRAM_SN_CTRL_HIGH_CNT_MAX_DEFAULT 0x4f /* 79 */
/* Type = rw */
-#define FRAM_SN_CTRL_HIGH_CNT_INITVAL_ADDR 0x8296 /* 8296 */
-#define FRAM_SN_CTRL_HIGH_CNT_INITVAL_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_CTRL_HIGH_CNT_INITVAL_ADDR 0x2068 /* 8296 */
+#define FRAM_SN_CTRL_HIGH_CNT_INITVAL_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_CTRL_HIGH_CNT_INITVAL_OFFSET 0x0 /* 0 */
-#define FRAM_SN_CTRL_HIGH_CNT_INITVAL_WIDTH 0x32 /* 32 */
-#define FRAM_SN_CTRL_HIGH_CNT_INITVAL_DEFAULT 0x79 /* 79 */
+#define FRAM_SN_CTRL_HIGH_CNT_INITVAL_WIDTH 0x20 /* 32 */
+#define FRAM_SN_CTRL_HIGH_CNT_INITVAL_DEFAULT 0x4f /* 79 */
/* Type = rw */
-#define FRAM_SN_CTRL_HIGH_CNT_INCVAL_ADDR 0x8300 /* 8300 */
-#define FRAM_SN_CTRL_HIGH_CNT_INCVAL_MASK 0x4294967295 /* 4294967295 */
+#define FRAM_SN_CTRL_HIGH_CNT_INCVAL_ADDR 0x206c /* 8300 */
+#define FRAM_SN_CTRL_HIGH_CNT_INCVAL_MASK 0xffffffff /* 4294967295 */
#define FRAM_SN_CTRL_HIGH_CNT_INCVAL_OFFSET 0x0 /* 0 */
-#define FRAM_SN_CTRL_HIGH_CNT_INCVAL_WIDTH 0x32 /* 32 */
+#define FRAM_SN_CTRL_HIGH_CNT_INCVAL_WIDTH 0x20 /* 32 */
#define FRAM_SN_CTRL_HIGH_CNT_INCVAL_DEFAULT 0x1 /* 1 */
/* Type = rw */
-#define FRAM_PROTOCOL_DEFINITION_ADDR 0x8704 /* 8704 */
-#define FRAM_PROTOCOL_DEFINITION_MASK 0x15 /* 15 */
+#define FRAM_PROTOCOL_DEFINITION_ADDR 0x2200 /* 8704 */
+#define FRAM_PROTOCOL_DEFINITION_MASK 0xf /* 15 */
#define FRAM_PROTOCOL_DEFINITION_OFFSET 0x0 /* 0 */
#define FRAM_PROTOCOL_DEFINITION_WIDTH 0x4 /* 4 */
#define FRAM_PROTOCOL_DEFINITION_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define FRAM_GEN_VLAN_TAG_ADDR 0x8704 /* 8704 */
-#define FRAM_GEN_VLAN_TAG_MASK 0x16 /* 16 */
+#define FRAM_GEN_VLAN_TAG_ADDR 0x2200 /* 8704 */
+#define FRAM_GEN_VLAN_TAG_MASK 0x10 /* 16 */
#define FRAM_GEN_VLAN_TAG_OFFSET 0x4 /* 4 */
#define FRAM_GEN_VLAN_TAG_WIDTH 0x1 /* 1 */
#define FRAM_GEN_VLAN_TAG_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define FRAM_SEL_IPV_ADDRESS_TYPE_ADDR 0x8704 /* 8704 */
-#define FRAM_SEL_IPV_ADDRESS_TYPE_MASK 0x96 /* 96 */
+#define FRAM_SEL_IPV_ADDRESS_TYPE_ADDR 0x2200 /* 8704 */
+#define FRAM_SEL_IPV_ADDRESS_TYPE_MASK 0x60 /* 96 */
#define FRAM_SEL_IPV_ADDRESS_TYPE_OFFSET 0x5 /* 5 */
#define FRAM_SEL_IPV_ADDRESS_TYPE_WIDTH 0x2 /* 2 */
#define FRAM_SEL_IPV_ADDRESS_TYPE_DEFAULT 0x0 /* 0 */
*-----------------------------------------------------------------------------
*/
/* Type = rw */
-#define FRAM_DRPFRAM_DATA_PC_ID_ADDR 0x16384 /* 16384 */
-#define FRAM_DRPFRAM_DATA_PC_ID_MASK 0x65535 /* 65535 */
+#define FRAM_DRPFRAM_DATA_PC_ID_ADDR 0x4000 /* 16384 */
+#define FRAM_DRPFRAM_DATA_PC_ID_MASK 0xffff /* 65535 */
#define FRAM_DRPFRAM_DATA_PC_ID_OFFSET 0x0 /* 0 */
-#define FRAM_DRPFRAM_DATA_PC_ID_WIDTH 0x16 /* 16 */
+#define FRAM_DRPFRAM_DATA_PC_ID_WIDTH 0x10 /* 16 */
#define FRAM_DRPFRAM_DATA_PC_ID_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define FRAM_DRPFRAM_DATA_MESSAGE_TYPE_ADDR 0x16384 /* 16384 */
-#define FRAM_DRPFRAM_DATA_MESSAGE_TYPE_MASK 0x16711680 /* 16711680 */
-#define FRAM_DRPFRAM_DATA_MESSAGE_TYPE_OFFSET 0x16 /* 16 */
+#define FRAM_DRPFRAM_DATA_MESSAGE_TYPE_ADDR 0x4000 /* 16384 */
+#define FRAM_DRPFRAM_DATA_MESSAGE_TYPE_MASK 0xff0000 /* 16711680 */
+#define FRAM_DRPFRAM_DATA_MESSAGE_TYPE_OFFSET 0x10 /* 16 */
#define FRAM_DRPFRAM_DATA_MESSAGE_TYPE_WIDTH 0x8 /* 8 */
#define FRAM_DRPFRAM_DATA_MESSAGE_TYPE_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define FRAM_DRPFRAM_DATA_ETHERNET_PORT_ADDR 0x16384 /* 16384 */
-#define FRAM_DRPFRAM_DATA_ETHERNET_PORT_MASK 0x4278190080 /* 4278190080 */
-#define FRAM_DRPFRAM_DATA_ETHERNET_PORT_OFFSET 0x24 /* 24 */
+#define FRAM_DRPFRAM_DATA_ETHERNET_PORT_ADDR 0x4000 /* 16384 */
+#define FRAM_DRPFRAM_DATA_ETHERNET_PORT_MASK 0xff000000 /* 4278190080 */
+#define FRAM_DRPFRAM_DATA_ETHERNET_PORT_OFFSET 0x18 /* 24 */
#define FRAM_DRPFRAM_DATA_ETHERNET_PORT_WIDTH 0x8 /* 8 */
#define FRAM_DRPFRAM_DATA_ETHERNET_PORT_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define FRAM_DRPFRAM_CTRL_PC_ID_ADDR 0x17408 /* 17408 */
-#define FRAM_DRPFRAM_CTRL_PC_ID_MASK 0x65535 /* 65535 */
+#define FRAM_DRPFRAM_CTRL_PC_ID_ADDR 0x4400 /* 17408 */
+#define FRAM_DRPFRAM_CTRL_PC_ID_MASK 0xffff /* 65535 */
#define FRAM_DRPFRAM_CTRL_PC_ID_OFFSET 0x0 /* 0 */
-#define FRAM_DRPFRAM_CTRL_PC_ID_WIDTH 0x16 /* 16 */
+#define FRAM_DRPFRAM_CTRL_PC_ID_WIDTH 0x10 /* 16 */
#define FRAM_DRPFRAM_CTRL_PC_ID_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define FRAM_DRPFRAM_CTRL_MESSAGE_TYPE_ADDR 0x17408 /* 17408 */
-#define FRAM_DRPFRAM_CTRL_MESSAGE_TYPE_MASK 0x16711680 /* 16711680 */
-#define FRAM_DRPFRAM_CTRL_MESSAGE_TYPE_OFFSET 0x16 /* 16 */
+#define FRAM_DRPFRAM_CTRL_MESSAGE_TYPE_ADDR 0x4400 /* 17408 */
+#define FRAM_DRPFRAM_CTRL_MESSAGE_TYPE_MASK 0xff0000 /* 16711680 */
+#define FRAM_DRPFRAM_CTRL_MESSAGE_TYPE_OFFSET 0x10 /* 16 */
#define FRAM_DRPFRAM_CTRL_MESSAGE_TYPE_WIDTH 0x8 /* 8 */
#define FRAM_DRPFRAM_CTRL_MESSAGE_TYPE_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define FRAM_DRPFRAM_CTRL_ETHERNET_PORT_ADDR 0x17408 /* 17408 */
-#define FRAM_DRPFRAM_CTRL_ETHERNET_PORT_MASK 0x4278190080 /* 4278190080 */
-#define FRAM_DRPFRAM_CTRL_ETHERNET_PORT_OFFSET 0x24 /* 24 */
+#define FRAM_DRPFRAM_CTRL_ETHERNET_PORT_ADDR 0x4400 /* 17408 */
+#define FRAM_DRPFRAM_CTRL_ETHERNET_PORT_MASK 0xff000000 /* 4278190080 */
+#define FRAM_DRPFRAM_CTRL_ETHERNET_PORT_OFFSET 0x18 /* 24 */
#define FRAM_DRPFRAM_CTRL_ETHERNET_PORT_WIDTH 0x8 /* 8 */
#define FRAM_DRPFRAM_CTRL_ETHERNET_PORT_DEFAULT 0x0 /* 0 */
/*-----------------------------------------------------------------------------
* C Header bank register definitions for bank roe_framer_v1_0_defm
* with prefix defm_ @ address 0x6000
- *-----------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
*/
/* Type = rw */
-#define DEFM_RESTART_ADDR 0x24576 /* 24576 */
+#define DEFM_RESTART_ADDR 0x6000 /* 24576 */
#define DEFM_RESTART_MASK 0x1 /* 1 */
#define DEFM_RESTART_OFFSET 0x0 /* 0 */
#define DEFM_RESTART_WIDTH 0x1 /* 1 */
#define DEFM_RESTART_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_READY_ADDR 0x24576 /* 24576 */
+#define DEFM_READY_ADDR 0x6000 /* 24576 */
#define DEFM_READY_MASK 0x2 /* 2 */
#define DEFM_READY_OFFSET 0x1 /* 1 */
#define DEFM_READY_WIDTH 0x1 /* 1 */
#define DEFM_READY_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define DEFM_ERR_PACKET_FILTER_ADDR 0x24580 /* 24580 */
+#define DEFM_ERR_PACKET_FILTER_ADDR 0x6004 /* 24580 */
#define DEFM_ERR_PACKET_FILTER_MASK 0x3 /* 3 */
#define DEFM_ERR_PACKET_FILTER_OFFSET 0x0 /* 0 */
#define DEFM_ERR_PACKET_FILTER_WIDTH 0x2 /* 2 */
#define DEFM_ERR_PACKET_FILTER_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define DEFM_DATA_PKT_MESSAGE_TYPE_ADDR 0x24584 /* 24584 */
-#define DEFM_DATA_PKT_MESSAGE_TYPE_MASK 0x255 /* 255 */
+#define DEFM_DATA_PKT_MESSAGE_TYPE_ADDR 0x6008 /* 24584 */
+#define DEFM_DATA_PKT_MESSAGE_TYPE_MASK 0xff /* 255 */
#define DEFM_DATA_PKT_MESSAGE_TYPE_OFFSET 0x0 /* 0 */
#define DEFM_DATA_PKT_MESSAGE_TYPE_WIDTH 0x8 /* 8 */
#define DEFM_DATA_PKT_MESSAGE_TYPE_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define DEFM_CTRL_PKT_MESSAGE_TYPE_ADDR 0x24588 /* 24588 */
-#define DEFM_CTRL_PKT_MESSAGE_TYPE_MASK 0x255 /* 255 */
+#define DEFM_CTRL_PKT_MESSAGE_TYPE_ADDR 0x600c /* 24588 */
+#define DEFM_CTRL_PKT_MESSAGE_TYPE_MASK 0xff /* 255 */
#define DEFM_CTRL_PKT_MESSAGE_TYPE_OFFSET 0x0 /* 0 */
#define DEFM_CTRL_PKT_MESSAGE_TYPE_WIDTH 0x8 /* 8 */
#define DEFM_CTRL_PKT_MESSAGE_TYPE_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define DEFM_SN_DATA_LOW_CNT_MIN_ADDR 0x24608 /* 24608 */
-#define DEFM_SN_DATA_LOW_CNT_MIN_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_DATA_LOW_CNT_MIN_ADDR 0x6020 /* 24608 */
+#define DEFM_SN_DATA_LOW_CNT_MIN_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_DATA_LOW_CNT_MIN_OFFSET 0x0 /* 0 */
-#define DEFM_SN_DATA_LOW_CNT_MIN_WIDTH 0x32 /* 32 */
+#define DEFM_SN_DATA_LOW_CNT_MIN_WIDTH 0x20 /* 32 */
#define DEFM_SN_DATA_LOW_CNT_MIN_DEFAULT 0x1 /* 1 */
/* Type = rw */
-#define DEFM_SN_DATA_LOW_CNT_MAX_ADDR 0x24612 /* 24612 */
-#define DEFM_SN_DATA_LOW_CNT_MAX_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_DATA_LOW_CNT_MAX_ADDR 0x6024 /* 24612 */
+#define DEFM_SN_DATA_LOW_CNT_MAX_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_DATA_LOW_CNT_MAX_OFFSET 0x0 /* 0 */
-#define DEFM_SN_DATA_LOW_CNT_MAX_WIDTH 0x32 /* 32 */
-#define DEFM_SN_DATA_LOW_CNT_MAX_DEFAULT 0x120 /* 120 */
+#define DEFM_SN_DATA_LOW_CNT_MAX_WIDTH 0x20 /* 32 */
+#define DEFM_SN_DATA_LOW_CNT_MAX_DEFAULT 0x78 /* 120 */
/* Type = rw */
-#define DEFM_SN_DATA_LOW_CNT_INCVAL_ADDR 0x24620 /* 24620 */
-#define DEFM_SN_DATA_LOW_CNT_INCVAL_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_DATA_LOW_CNT_INCVAL_ADDR 0x602c /* 24620 */
+#define DEFM_SN_DATA_LOW_CNT_INCVAL_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_DATA_LOW_CNT_INCVAL_OFFSET 0x0 /* 0 */
-#define DEFM_SN_DATA_LOW_CNT_INCVAL_WIDTH 0x32 /* 32 */
+#define DEFM_SN_DATA_LOW_CNT_INCVAL_WIDTH 0x20 /* 32 */
#define DEFM_SN_DATA_LOW_CNT_INCVAL_DEFAULT 0x1 /* 1 */
/* Type = rw */
-#define DEFM_SN_DATA_HIGH_CNT_MIN_ADDR 0x24624 /* 24624 */
-#define DEFM_SN_DATA_HIGH_CNT_MIN_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_DATA_HIGH_CNT_MIN_ADDR 0x6030 /* 24624 */
+#define DEFM_SN_DATA_HIGH_CNT_MIN_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_DATA_HIGH_CNT_MIN_OFFSET 0x0 /* 0 */
-#define DEFM_SN_DATA_HIGH_CNT_MIN_WIDTH 0x32 /* 32 */
+#define DEFM_SN_DATA_HIGH_CNT_MIN_WIDTH 0x20 /* 32 */
#define DEFM_SN_DATA_HIGH_CNT_MIN_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define DEFM_SN_DATA_HIGH_CNT_MAX_ADDR 0x24628 /* 24628 */
-#define DEFM_SN_DATA_HIGH_CNT_MAX_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_DATA_HIGH_CNT_MAX_ADDR 0x6034 /* 24628 */
+#define DEFM_SN_DATA_HIGH_CNT_MAX_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_DATA_HIGH_CNT_MAX_OFFSET 0x0 /* 0 */
-#define DEFM_SN_DATA_HIGH_CNT_MAX_WIDTH 0x32 /* 32 */
-#define DEFM_SN_DATA_HIGH_CNT_MAX_DEFAULT 0x79 /* 79 */
+#define DEFM_SN_DATA_HIGH_CNT_MAX_WIDTH 0x20 /* 32 */
+#define DEFM_SN_DATA_HIGH_CNT_MAX_DEFAULT 0x4f /* 79 */
/* Type = rw */
-#define DEFM_SN_DATA_HIGH_CNT_INCVAL_ADDR 0x24636 /* 24636 */
-#define DEFM_SN_DATA_HIGH_CNT_INCVAL_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_DATA_HIGH_CNT_INCVAL_ADDR 0x603c /* 24636 */
+#define DEFM_SN_DATA_HIGH_CNT_INCVAL_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_DATA_HIGH_CNT_INCVAL_OFFSET 0x0 /* 0 */
-#define DEFM_SN_DATA_HIGH_CNT_INCVAL_WIDTH 0x32 /* 32 */
+#define DEFM_SN_DATA_HIGH_CNT_INCVAL_WIDTH 0x20 /* 32 */
#define DEFM_SN_DATA_HIGH_CNT_INCVAL_DEFAULT 0x1 /* 1 */
/* Type = rw */
-#define DEFM_SN_CTRL_LOW_CNT_MIN_ADDR 0x24656 /* 24656 */
-#define DEFM_SN_CTRL_LOW_CNT_MIN_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_CTRL_LOW_CNT_MIN_ADDR 0x6050 /* 24656 */
+#define DEFM_SN_CTRL_LOW_CNT_MIN_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_CTRL_LOW_CNT_MIN_OFFSET 0x0 /* 0 */
-#define DEFM_SN_CTRL_LOW_CNT_MIN_WIDTH 0x32 /* 32 */
+#define DEFM_SN_CTRL_LOW_CNT_MIN_WIDTH 0x20 /* 32 */
#define DEFM_SN_CTRL_LOW_CNT_MIN_DEFAULT 0x1 /* 1 */
/* Type = rw */
-#define DEFM_SN_CTRL_LOW_CNT_MAX_ADDR 0x24660 /* 24660 */
-#define DEFM_SN_CTRL_LOW_CNT_MAX_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_CTRL_LOW_CNT_MAX_ADDR 0x6054 /* 24660 */
+#define DEFM_SN_CTRL_LOW_CNT_MAX_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_CTRL_LOW_CNT_MAX_OFFSET 0x0 /* 0 */
-#define DEFM_SN_CTRL_LOW_CNT_MAX_WIDTH 0x32 /* 32 */
-#define DEFM_SN_CTRL_LOW_CNT_MAX_DEFAULT 0x120 /* 120 */
+#define DEFM_SN_CTRL_LOW_CNT_MAX_WIDTH 0x20 /* 32 */
+#define DEFM_SN_CTRL_LOW_CNT_MAX_DEFAULT 0x78 /* 120 */
/* Type = rw */
-#define DEFM_SN_CTRL_LOW_CNT_INCVAL_ADDR 0x24668 /* 24668 */
-#define DEFM_SN_CTRL_LOW_CNT_INCVAL_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_CTRL_LOW_CNT_INCVAL_ADDR 0x605c /* 24668 */
+#define DEFM_SN_CTRL_LOW_CNT_INCVAL_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_CTRL_LOW_CNT_INCVAL_OFFSET 0x0 /* 0 */
-#define DEFM_SN_CTRL_LOW_CNT_INCVAL_WIDTH 0x32 /* 32 */
+#define DEFM_SN_CTRL_LOW_CNT_INCVAL_WIDTH 0x20 /* 32 */
#define DEFM_SN_CTRL_LOW_CNT_INCVAL_DEFAULT 0x1 /* 1 */
/* Type = rw */
-#define DEFM_SN_CTRL_HIGH_CNT_MIN_ADDR 0x24672 /* 24672 */
-#define DEFM_SN_CTRL_HIGH_CNT_MIN_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_CTRL_HIGH_CNT_MIN_ADDR 0x6060 /* 24672 */
+#define DEFM_SN_CTRL_HIGH_CNT_MIN_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_CTRL_HIGH_CNT_MIN_OFFSET 0x0 /* 0 */
-#define DEFM_SN_CTRL_HIGH_CNT_MIN_WIDTH 0x32 /* 32 */
+#define DEFM_SN_CTRL_HIGH_CNT_MIN_WIDTH 0x20 /* 32 */
#define DEFM_SN_CTRL_HIGH_CNT_MIN_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define DEFM_SN_CTRL_HIGH_CNT_MAX_ADDR 0x24676 /* 24676 */
-#define DEFM_SN_CTRL_HIGH_CNT_MAX_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_CTRL_HIGH_CNT_MAX_ADDR 0x6064 /* 24676 */
+#define DEFM_SN_CTRL_HIGH_CNT_MAX_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_CTRL_HIGH_CNT_MAX_OFFSET 0x0 /* 0 */
-#define DEFM_SN_CTRL_HIGH_CNT_MAX_WIDTH 0x32 /* 32 */
-#define DEFM_SN_CTRL_HIGH_CNT_MAX_DEFAULT 0x79 /* 79 */
+#define DEFM_SN_CTRL_HIGH_CNT_MAX_WIDTH 0x20 /* 32 */
+#define DEFM_SN_CTRL_HIGH_CNT_MAX_DEFAULT 0x4f /* 79 */
/* Type = rw */
-#define DEFM_SN_CTRL_HIGH_CNT_INCVAL_ADDR 0x24684 /* 24684 */
-#define DEFM_SN_CTRL_HIGH_CNT_INCVAL_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_SN_CTRL_HIGH_CNT_INCVAL_ADDR 0x606c /* 24684 */
+#define DEFM_SN_CTRL_HIGH_CNT_INCVAL_MASK 0xffffffff /* 4294967295 */
#define DEFM_SN_CTRL_HIGH_CNT_INCVAL_OFFSET 0x0 /* 0 */
-#define DEFM_SN_CTRL_HIGH_CNT_INCVAL_WIDTH 0x32 /* 32 */
+#define DEFM_SN_CTRL_HIGH_CNT_INCVAL_WIDTH 0x20 /* 32 */
#define DEFM_SN_CTRL_HIGH_CNT_INCVAL_DEFAULT 0x1 /* 1 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W0_31_0_ADDR 0x24832 /* 24832 */
-#define DEFM_USER_DATA_FILTER_W0_31_0_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W0_31_0_ADDR 0x6100 /* 24832 */
+#define DEFM_USER_DATA_FILTER_W0_31_0_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W0_31_0_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W0_31_0_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W0_31_0_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W0_31_0_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W0_31_0_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W0_63_32_ADDR 0x24836 /* 24836 */
-#define DEFM_USER_DATA_FILTER_W0_63_32_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W0_63_32_ADDR 0x6104 /* 24836 */
+#define DEFM_USER_DATA_FILTER_W0_63_32_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W0_63_32_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W0_63_32_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W0_63_32_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W0_63_32_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W0_63_32_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W0_95_64_ADDR 0x24840 /* 24840 */
-#define DEFM_USER_DATA_FILTER_W0_95_64_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W0_95_64_ADDR 0x6108 /* 24840 */
+#define DEFM_USER_DATA_FILTER_W0_95_64_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W0_95_64_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W0_95_64_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W0_95_64_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W0_95_64_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W0_95_64_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W0_127_96_ADDR 0x24844 /* 24844 */
-#define DEFM_USER_DATA_FILTER_W0_127_96_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W0_127_96_ADDR 0x610c /* 24844 */
+#define DEFM_USER_DATA_FILTER_W0_127_96_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W0_127_96_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W0_127_96_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W0_127_96_DEFAULT 0x4294966958 /* 4294966958 */
+#define DEFM_USER_DATA_FILTER_W0_127_96_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W0_127_96_DEFAULT 0xfffffeae /* 4294966958 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W0_MASK_ADDR 0x24848 /* 24848 */
-#define DEFM_USER_DATA_FILTER_W0_MASK_MASK 0x65535 /* 65535 */
+#define DEFM_USER_DATA_FILTER_W0_MASK_ADDR 0x6110 /* 24848 */
+#define DEFM_USER_DATA_FILTER_W0_MASK_MASK 0xffff /* 65535 */
#define DEFM_USER_DATA_FILTER_W0_MASK_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W0_MASK_WIDTH 0x16 /* 16 */
-#define DEFM_USER_DATA_FILTER_W0_MASK_DEFAULT 0x53247 /* 53247 */
+#define DEFM_USER_DATA_FILTER_W0_MASK_WIDTH 0x10 /* 16 */
+#define DEFM_USER_DATA_FILTER_W0_MASK_DEFAULT 0xcfff /* 53247 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W1_31_0_ADDR 0x24864 /* 24864 */
-#define DEFM_USER_DATA_FILTER_W1_31_0_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W1_31_0_ADDR 0x6120 /* 24864 */
+#define DEFM_USER_DATA_FILTER_W1_31_0_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W1_31_0_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W1_31_0_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W1_31_0_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W1_31_0_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W1_31_0_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W1_63_32_ADDR 0x24868 /* 24868 */
-#define DEFM_USER_DATA_FILTER_W1_63_32_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W1_63_32_ADDR 0x6124 /* 24868 */
+#define DEFM_USER_DATA_FILTER_W1_63_32_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W1_63_32_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W1_63_32_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W1_63_32_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W1_63_32_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W1_63_32_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W1_95_64_ADDR 0x24872 /* 24872 */
-#define DEFM_USER_DATA_FILTER_W1_95_64_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W1_95_64_ADDR 0x6128 /* 24872 */
+#define DEFM_USER_DATA_FILTER_W1_95_64_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W1_95_64_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W1_95_64_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W1_95_64_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W1_95_64_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W1_95_64_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W1_127_96_ADDR 0x24876 /* 24876 */
-#define DEFM_USER_DATA_FILTER_W1_127_96_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W1_127_96_ADDR 0x612c /* 24876 */
+#define DEFM_USER_DATA_FILTER_W1_127_96_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W1_127_96_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W1_127_96_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W1_127_96_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W1_127_96_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W1_127_96_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W1_MASK_ADDR 0x24880 /* 24880 */
-#define DEFM_USER_DATA_FILTER_W1_MASK_MASK 0x65535 /* 65535 */
+#define DEFM_USER_DATA_FILTER_W1_MASK_ADDR 0x6130 /* 24880 */
+#define DEFM_USER_DATA_FILTER_W1_MASK_MASK 0xffff /* 65535 */
#define DEFM_USER_DATA_FILTER_W1_MASK_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W1_MASK_WIDTH 0x16 /* 16 */
-#define DEFM_USER_DATA_FILTER_W1_MASK_DEFAULT 0x65535 /* 65535 */
+#define DEFM_USER_DATA_FILTER_W1_MASK_WIDTH 0x10 /* 16 */
+#define DEFM_USER_DATA_FILTER_W1_MASK_DEFAULT 0xffff /* 65535 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W2_31_0_ADDR 0x24896 /* 24896 */
-#define DEFM_USER_DATA_FILTER_W2_31_0_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W2_31_0_ADDR 0x6140 /* 24896 */
+#define DEFM_USER_DATA_FILTER_W2_31_0_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W2_31_0_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W2_31_0_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W2_31_0_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W2_31_0_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W2_31_0_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W2_63_32_ADDR 0x24900 /* 24900 */
-#define DEFM_USER_DATA_FILTER_W2_63_32_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W2_63_32_ADDR 0x6144 /* 24900 */
+#define DEFM_USER_DATA_FILTER_W2_63_32_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W2_63_32_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W2_63_32_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W2_63_32_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W2_63_32_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W2_63_32_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W2_95_64_ADDR 0x24904 /* 24904 */
-#define DEFM_USER_DATA_FILTER_W2_95_64_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W2_95_64_ADDR 0x6148 /* 24904 */
+#define DEFM_USER_DATA_FILTER_W2_95_64_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W2_95_64_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W2_95_64_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W2_95_64_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W2_95_64_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W2_95_64_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W2_127_96_ADDR 0x24908 /* 24908 */
-#define DEFM_USER_DATA_FILTER_W2_127_96_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W2_127_96_ADDR 0x614c /* 24908 */
+#define DEFM_USER_DATA_FILTER_W2_127_96_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W2_127_96_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W2_127_96_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W2_127_96_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W2_127_96_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W2_127_96_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W2_MASK_ADDR 0x24912 /* 24912 */
-#define DEFM_USER_DATA_FILTER_W2_MASK_MASK 0x65535 /* 65535 */
+#define DEFM_USER_DATA_FILTER_W2_MASK_ADDR 0x6150 /* 24912 */
+#define DEFM_USER_DATA_FILTER_W2_MASK_MASK 0xffff /* 65535 */
#define DEFM_USER_DATA_FILTER_W2_MASK_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W2_MASK_WIDTH 0x16 /* 16 */
-#define DEFM_USER_DATA_FILTER_W2_MASK_DEFAULT 0x65535 /* 65535 */
+#define DEFM_USER_DATA_FILTER_W2_MASK_WIDTH 0x10 /* 16 */
+#define DEFM_USER_DATA_FILTER_W2_MASK_DEFAULT 0xffff /* 65535 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W3_31_0_ADDR 0x24928 /* 24928 */
-#define DEFM_USER_DATA_FILTER_W3_31_0_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W3_31_0_ADDR 0x6160 /* 24928 */
+#define DEFM_USER_DATA_FILTER_W3_31_0_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W3_31_0_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W3_31_0_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W3_31_0_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W3_31_0_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W3_31_0_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W3_63_32_ADDR 0x24932 /* 24932 */
-#define DEFM_USER_DATA_FILTER_W3_63_32_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W3_63_32_ADDR 0x6164 /* 24932 */
+#define DEFM_USER_DATA_FILTER_W3_63_32_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W3_63_32_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W3_63_32_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W3_63_32_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W3_63_32_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W3_63_32_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W3_95_64_ADDR 0x24936 /* 24936 */
-#define DEFM_USER_DATA_FILTER_W3_95_64_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W3_95_64_ADDR 0x6168 /* 24936 */
+#define DEFM_USER_DATA_FILTER_W3_95_64_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W3_95_64_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W3_95_64_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W3_95_64_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W3_95_64_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W3_95_64_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W3_127_96_ADDR 0x24940 /* 24940 */
-#define DEFM_USER_DATA_FILTER_W3_127_96_MASK 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W3_127_96_ADDR 0x616c /* 24940 */
+#define DEFM_USER_DATA_FILTER_W3_127_96_MASK 0xffffffff /* 4294967295 */
#define DEFM_USER_DATA_FILTER_W3_127_96_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W3_127_96_WIDTH 0x32 /* 32 */
-#define DEFM_USER_DATA_FILTER_W3_127_96_DEFAULT 0x4294967295 /* 4294967295 */
+#define DEFM_USER_DATA_FILTER_W3_127_96_WIDTH 0x20 /* 32 */
+#define DEFM_USER_DATA_FILTER_W3_127_96_DEFAULT 0xffffffff /* 4294967295 */
/* Type = rwpdef */
-#define DEFM_USER_DATA_FILTER_W3_MASK_ADDR 0x24944 /* 24944 */
-#define DEFM_USER_DATA_FILTER_W3_MASK_MASK 0x65535 /* 65535 */
+#define DEFM_USER_DATA_FILTER_W3_MASK_ADDR 0x6170 /* 24944 */
+#define DEFM_USER_DATA_FILTER_W3_MASK_MASK 0xffff /* 65535 */
#define DEFM_USER_DATA_FILTER_W3_MASK_OFFSET 0x0 /* 0 */
-#define DEFM_USER_DATA_FILTER_W3_MASK_WIDTH 0x16 /* 16 */
-#define DEFM_USER_DATA_FILTER_W3_MASK_DEFAULT 0x65535 /* 65535 */
+#define DEFM_USER_DATA_FILTER_W3_MASK_WIDTH 0x10 /* 16 */
+#define DEFM_USER_DATA_FILTER_W3_MASK_DEFAULT 0xffff /* 65535 */
/*-----------------------------------------------------------------------------
* C Header bank register definitions for bank roe_framer_v1_0_defm_drp
*-----------------------------------------------------------------------------
*/
/* Type = rw */
-#define DEFM_DRPDEFM_DATA_PC_ID_ADDR 0x32768 /* 32768 */
-#define DEFM_DRPDEFM_DATA_PC_ID_MASK 0x65535 /* 65535 */
+#define DEFM_DRPDEFM_DATA_PC_ID_ADDR 0x8000 /* 32768 */
+#define DEFM_DRPDEFM_DATA_PC_ID_MASK 0xffff /* 65535 */
#define DEFM_DRPDEFM_DATA_PC_ID_OFFSET 0x0 /* 0 */
-#define DEFM_DRPDEFM_DATA_PC_ID_WIDTH 0x16 /* 16 */
+#define DEFM_DRPDEFM_DATA_PC_ID_WIDTH 0x10 /* 16 */
#define DEFM_DRPDEFM_DATA_PC_ID_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define DEFM_DRPDEFM_CTRL_PC_ID_ADDR 0x33792 /* 33792 */
-#define DEFM_DRPDEFM_CTRL_PC_ID_MASK 0x65535 /* 65535 */
+#define DEFM_DRPDEFM_CTRL_PC_ID_ADDR 0x8400 /* 33792 */
+#define DEFM_DRPDEFM_CTRL_PC_ID_MASK 0xffff /* 65535 */
#define DEFM_DRPDEFM_CTRL_PC_ID_OFFSET 0x0 /* 0 */
-#define DEFM_DRPDEFM_CTRL_PC_ID_WIDTH 0x16 /* 16 */
+#define DEFM_DRPDEFM_CTRL_PC_ID_WIDTH 0x10 /* 16 */
#define DEFM_DRPDEFM_CTRL_PC_ID_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_LATENCY_ADDR 0x34816 /* 34816 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_LATENCY_MASK 0x16777215 /* 16777215 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_LATENCY_ADDR 0x8800 /* 34816 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_LATENCY_MASK 0xffffff /* 16777215 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_LATENCY_OFFSET 0x0 /* 0 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_LATENCY_WIDTH 0x24 /* 24 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_LATENCY_WIDTH 0x18 /* 24 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_LATENCY_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_ALIGNMENT_ADDR 0x34816 /* 34816 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_ALIGNMENT_MASK 0x16777216 /* 16777216 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_ALIGNMENT_OFFSET 0x24 /* 24 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_ALIGNMENT_ADDR 0x8800 /* 34816 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_ALIGNMENT_MASK 0x1000000 /* 16777216 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_ALIGNMENT_OFFSET 0x18 /* 24 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_ALIGNMENT_WIDTH 0x1 /* 1 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_ALIGNMENT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_OVERFLOW_ADDR 0x34816 /* 34816 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_OVERFLOW_MASK 0x33554432 /* 33554432 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_OVERFLOW_OFFSET 0x25 /* 25 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_OVERFLOW_ADDR 0x8800 /* 34816 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_OVERFLOW_MASK 0x2000000 /* 33554432 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_OVERFLOW_OFFSET 0x19 /* 25 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_OVERFLOW_WIDTH 0x1 /* 1 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_OVERFLOW_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_UNDERFLOW_ADDR 0x34816 /* 34816 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_UNDERFLOW_MASK 0x67108864 /* 67108864 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_UNDERFLOW_OFFSET 0x26 /* 26 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_UNDERFLOW_ADDR 0x8800 /* 34816 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_UNDERFLOW_MASK 0x4000000 /* 67108864 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_UNDERFLOW_OFFSET 0x1a /* 26 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_UNDERFLOW_WIDTH 0x1 /* 1 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_UNDERFLOW_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_REGULAR_ADDR 0x34816 /* 34816 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_REGULAR_MASK 0x134217728 /* 134217728 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_REGULAR_OFFSET 0x27 /* 27 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_REGULAR_ADDR 0x8800 /* 34816 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_REGULAR_MASK 0x8000000 /* 134217728 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_REGULAR_OFFSET 0x1b /* 27 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_REGULAR_WIDTH 0x1 /* 1 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_REGULAR_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_RWIN_ADDR 0x34816 /* 34816 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_RWIN_MASK 0x4026531840 /* 4026531840 */
-#define DEFM_DRPDEFM_DATA_BUFFER_STATE_RWIN_OFFSET 0x28 /* 28 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_RWIN_ADDR 0x8800 /* 34816 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_RWIN_MASK 0xf0000000 /* 4026531840 */
+#define DEFM_DRPDEFM_DATA_BUFFER_STATE_RWIN_OFFSET 0x1c /* 28 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_RWIN_WIDTH 0x4 /* 4 */
#define DEFM_DRPDEFM_DATA_BUFFER_STATE_RWIN_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_LATENCY_ADDR 0x38912 /* 38912 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_LATENCY_MASK 0x16777215 /* 16777215 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_LATENCY_ADDR 0x9800 /* 38912 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_LATENCY_MASK 0xffffff /* 16777215 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_LATENCY_OFFSET 0x0 /* 0 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_LATENCY_WIDTH 0x24 /* 24 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_LATENCY_WIDTH 0x18 /* 24 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_LATENCY_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_ALIGNMENT_ADDR 0x38912 /* 38912 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_ALIGNMENT_MASK 0x16777216 /* 16777216 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_ALIGNMENT_OFFSET 0x24 /* 24 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_ALIGNMENT_ADDR 0x9800 /* 38912 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_ALIGNMENT_MASK 0x1000000 /* 16777216 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_ALIGNMENT_OFFSET 0x18 /* 24 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_ALIGNMENT_WIDTH 0x1 /* 1 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_ALIGNMENT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_OVERFLOW_ADDR 0x38912 /* 38912 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_OVERFLOW_MASK 0x33554432 /* 33554432 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_OVERFLOW_OFFSET 0x25 /* 25 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_OVERFLOW_ADDR 0x9800 /* 38912 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_OVERFLOW_MASK 0x2000000 /* 33554432 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_OVERFLOW_OFFSET 0x19 /* 25 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_OVERFLOW_WIDTH 0x1 /* 1 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_OVERFLOW_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_UNDERFLOW_ADDR 0x38912 /* 38912 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_UNDERFLOW_MASK 0x67108864 /* 67108864 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_UNDERFLOW_OFFSET 0x26 /* 26 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_UNDERFLOW_ADDR 0x9800 /* 38912 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_UNDERFLOW_MASK 0x4000000 /* 67108864 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_UNDERFLOW_OFFSET 0x1a /* 26 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_UNDERFLOW_WIDTH 0x1 /* 1 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_UNDERFLOW_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_REGULAR_ADDR 0x38912 /* 38912 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_REGULAR_MASK 0x134217728 /* 134217728 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_REGULAR_OFFSET 0x27 /* 27 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_REGULAR_ADDR 0x9800 /* 38912 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_REGULAR_MASK 0x8000000 /* 134217728 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_REGULAR_OFFSET 0x1b /* 27 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_REGULAR_WIDTH 0x1 /* 1 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_REGULAR_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_RWIN_ADDR 0x38912 /* 38912 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_RWIN_MASK 0x4026531840 /* 4026531840 */
-#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_RWIN_OFFSET 0x28 /* 28 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_RWIN_ADDR 0x9800 /* 38912 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_RWIN_MASK 0xf0000000 /* 4026531840 */
+#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_RWIN_OFFSET 0x1c /* 28 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_RWIN_WIDTH 0x4 /* 4 */
#define DEFM_DRPDEFM_CTRL_BUFFER_STATE_RWIN_DEFAULT 0x0 /* 0 */
*-----------------------------------------------------------------------------
*/
/* Type = rwpdef */
-#define ETH_DEST_ADDR_31_0_ADDR 0x40960 /* 40960 */
-#define ETH_DEST_ADDR_31_0_MASK 0x4294967295 /* 4294967295 */
+#define ETH_DEST_ADDR_31_0_ADDR 0xa000 /* 40960 */
+#define ETH_DEST_ADDR_31_0_MASK 0xffffffff /* 4294967295 */
#define ETH_DEST_ADDR_31_0_OFFSET 0x0 /* 0 */
-#define ETH_DEST_ADDR_31_0_WIDTH 0x32 /* 32 */
+#define ETH_DEST_ADDR_31_0_WIDTH 0x20 /* 32 */
#define ETH_DEST_ADDR_31_0_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_DEST_ADDR_47_32_ADDR 0x40964 /* 40964 */
-#define ETH_DEST_ADDR_47_32_MASK 0x65535 /* 65535 */
+#define ETH_DEST_ADDR_47_32_ADDR 0xa004 /* 40964 */
+#define ETH_DEST_ADDR_47_32_MASK 0xffff /* 65535 */
#define ETH_DEST_ADDR_47_32_OFFSET 0x0 /* 0 */
-#define ETH_DEST_ADDR_47_32_WIDTH 0x16 /* 16 */
+#define ETH_DEST_ADDR_47_32_WIDTH 0x10 /* 16 */
#define ETH_DEST_ADDR_47_32_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_SRC_ADDR_31_0_ADDR 0x40968 /* 40968 */
-#define ETH_SRC_ADDR_31_0_MASK 0x4294967295 /* 4294967295 */
+#define ETH_SRC_ADDR_31_0_ADDR 0xa008 /* 40968 */
+#define ETH_SRC_ADDR_31_0_MASK 0xffffffff /* 4294967295 */
#define ETH_SRC_ADDR_31_0_OFFSET 0x0 /* 0 */
-#define ETH_SRC_ADDR_31_0_WIDTH 0x32 /* 32 */
+#define ETH_SRC_ADDR_31_0_WIDTH 0x20 /* 32 */
#define ETH_SRC_ADDR_31_0_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_SRC_ADDR_47_32_ADDR 0x40972 /* 40972 */
-#define ETH_SRC_ADDR_47_32_MASK 0x65535 /* 65535 */
+#define ETH_SRC_ADDR_47_32_ADDR 0xa00c /* 40972 */
+#define ETH_SRC_ADDR_47_32_MASK 0xffff /* 65535 */
#define ETH_SRC_ADDR_47_32_OFFSET 0x0 /* 0 */
-#define ETH_SRC_ADDR_47_32_WIDTH 0x16 /* 16 */
+#define ETH_SRC_ADDR_47_32_WIDTH 0x10 /* 16 */
#define ETH_SRC_ADDR_47_32_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_VLAN_ID_ADDR 0x40976 /* 40976 */
-#define ETH_VLAN_ID_MASK 0x4095 /* 4095 */
+#define ETH_VLAN_ID_ADDR 0xa010 /* 40976 */
+#define ETH_VLAN_ID_MASK 0xfff /* 4095 */
#define ETH_VLAN_ID_OFFSET 0x0 /* 0 */
-#define ETH_VLAN_ID_WIDTH 0x12 /* 12 */
+#define ETH_VLAN_ID_WIDTH 0xc /* 12 */
#define ETH_VLAN_ID_DEFAULT 0x1 /* 1 */
/* Type = rwpdef */
-#define ETH_VLAN_DEI_ADDR 0x40976 /* 40976 */
-#define ETH_VLAN_DEI_MASK 0x4096 /* 4096 */
-#define ETH_VLAN_DEI_OFFSET 0x12 /* 12 */
+#define ETH_VLAN_DEI_ADDR 0xa010 /* 40976 */
+#define ETH_VLAN_DEI_MASK 0x1000 /* 4096 */
+#define ETH_VLAN_DEI_OFFSET 0xc /* 12 */
#define ETH_VLAN_DEI_WIDTH 0x1 /* 1 */
#define ETH_VLAN_DEI_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_VLAN_PCP_ADDR 0x40976 /* 40976 */
-#define ETH_VLAN_PCP_MASK 0x57344 /* 57344 */
-#define ETH_VLAN_PCP_OFFSET 0x13 /* 13 */
+#define ETH_VLAN_PCP_ADDR 0xa010 /* 40976 */
+#define ETH_VLAN_PCP_MASK 0xe000 /* 57344 */
+#define ETH_VLAN_PCP_OFFSET 0xd /* 13 */
#define ETH_VLAN_PCP_WIDTH 0x3 /* 3 */
#define ETH_VLAN_PCP_DEFAULT 0x7 /* 7 */
/* Type = rw */
-#define ETH_IPV4_VERSION_ADDR 0x41008 /* 41008 */
-#define ETH_IPV4_VERSION_MASK 0x15 /* 15 */
+#define ETH_IPV4_VERSION_ADDR 0xa030 /* 41008 */
+#define ETH_IPV4_VERSION_MASK 0xf /* 15 */
#define ETH_IPV4_VERSION_OFFSET 0x0 /* 0 */
#define ETH_IPV4_VERSION_WIDTH 0x4 /* 4 */
#define ETH_IPV4_VERSION_DEFAULT 0x4 /* 4 */
/* Type = rw */
-#define ETH_IPV4_IHL_ADDR 0x41008 /* 41008 */
-#define ETH_IPV4_IHL_MASK 0x240 /* 240 */
+#define ETH_IPV4_IHL_ADDR 0xa030 /* 41008 */
+#define ETH_IPV4_IHL_MASK 0xf0 /* 240 */
#define ETH_IPV4_IHL_OFFSET 0x4 /* 4 */
#define ETH_IPV4_IHL_WIDTH 0x4 /* 4 */
#define ETH_IPV4_IHL_DEFAULT 0x5 /* 5 */
/* Type = rw */
-#define ETH_IPV4_DSCP_ADDR 0x41012 /* 41012 */
-#define ETH_IPV4_DSCP_MASK 0x63 /* 63 */
+#define ETH_IPV4_DSCP_ADDR 0xa034 /* 41012 */
+#define ETH_IPV4_DSCP_MASK 0x3f /* 63 */
#define ETH_IPV4_DSCP_OFFSET 0x0 /* 0 */
#define ETH_IPV4_DSCP_WIDTH 0x6 /* 6 */
-#define ETH_IPV4_DSCP_DEFAULT 0x46 /* 46 */
+#define ETH_IPV4_DSCP_DEFAULT 0x2e /* 46 */
/* Type = rw */
-#define ETH_IPV4_ECN_ADDR 0x41012 /* 41012 */
-#define ETH_IPV4_ECN_MASK 0x192 /* 192 */
+#define ETH_IPV4_ECN_ADDR 0xa034 /* 41012 */
+#define ETH_IPV4_ECN_MASK 0xc0 /* 192 */
#define ETH_IPV4_ECN_OFFSET 0x6 /* 6 */
#define ETH_IPV4_ECN_WIDTH 0x2 /* 2 */
#define ETH_IPV4_ECN_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define ETH_IPV4_ID_ADDR 0x41016 /* 41016 */
-#define ETH_IPV4_ID_MASK 0x65535 /* 65535 */
+#define ETH_IPV4_ID_ADDR 0xa038 /* 41016 */
+#define ETH_IPV4_ID_MASK 0xffff /* 65535 */
#define ETH_IPV4_ID_OFFSET 0x0 /* 0 */
-#define ETH_IPV4_ID_WIDTH 0x16 /* 16 */
+#define ETH_IPV4_ID_WIDTH 0x10 /* 16 */
#define ETH_IPV4_ID_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define ETH_IPV4_FLAGS_ADDR 0x41020 /* 41020 */
+#define ETH_IPV4_FLAGS_ADDR 0xa03c /* 41020 */
#define ETH_IPV4_FLAGS_MASK 0x7 /* 7 */
#define ETH_IPV4_FLAGS_OFFSET 0x0 /* 0 */
#define ETH_IPV4_FLAGS_WIDTH 0x3 /* 3 */
#define ETH_IPV4_FLAGS_DEFAULT 0x2 /* 2 */
/* Type = rw */
-#define ETH_IPV4_FRAGMENT_OFFSET_ADDR 0x41020 /* 41020 */
-#define ETH_IPV4_FRAGMENT_OFFSET_MASK 0x131064 /* 131064 */
+#define ETH_IPV4_FRAGMENT_OFFSET_ADDR 0xa03c /* 41020 */
+#define ETH_IPV4_FRAGMENT_OFFSET_MASK 0x1fff8 /* 131064 */
#define ETH_IPV4_FRAGMENT_OFFSET_OFFSET 0x3 /* 3 */
-#define ETH_IPV4_FRAGMENT_OFFSET_WIDTH 0x14 /* 14 */
+#define ETH_IPV4_FRAGMENT_OFFSET_WIDTH 0xe /* 14 */
#define ETH_IPV4_FRAGMENT_OFFSET_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define ETH_IPV4_TIME_TO_LIVE_ADDR 0x41024 /* 41024 */
-#define ETH_IPV4_TIME_TO_LIVE_MASK 0x255 /* 255 */
+#define ETH_IPV4_TIME_TO_LIVE_ADDR 0xa040 /* 41024 */
+#define ETH_IPV4_TIME_TO_LIVE_MASK 0xff /* 255 */
#define ETH_IPV4_TIME_TO_LIVE_OFFSET 0x0 /* 0 */
#define ETH_IPV4_TIME_TO_LIVE_WIDTH 0x8 /* 8 */
-#define ETH_IPV4_TIME_TO_LIVE_DEFAULT 0x64 /* 64 */
+#define ETH_IPV4_TIME_TO_LIVE_DEFAULT 0x40 /* 64 */
/* Type = rw */
-#define ETH_IPV4_PROTOCOL_ADDR 0x41028 /* 41028 */
-#define ETH_IPV4_PROTOCOL_MASK 0x255 /* 255 */
+#define ETH_IPV4_PROTOCOL_ADDR 0xa044 /* 41028 */
+#define ETH_IPV4_PROTOCOL_MASK 0xff /* 255 */
#define ETH_IPV4_PROTOCOL_OFFSET 0x0 /* 0 */
#define ETH_IPV4_PROTOCOL_WIDTH 0x8 /* 8 */
-#define ETH_IPV4_PROTOCOL_DEFAULT 0x17 /* 17 */
+#define ETH_IPV4_PROTOCOL_DEFAULT 0x11 /* 17 */
/* Type = rwpdef */
-#define ETH_IPV4_SOURCE_ADD_ADDR 0x41032 /* 41032 */
-#define ETH_IPV4_SOURCE_ADD_MASK 0x4294967295 /* 4294967295 */
+#define ETH_IPV4_SOURCE_ADD_ADDR 0xa048 /* 41032 */
+#define ETH_IPV4_SOURCE_ADD_MASK 0xffffffff /* 4294967295 */
#define ETH_IPV4_SOURCE_ADD_OFFSET 0x0 /* 0 */
-#define ETH_IPV4_SOURCE_ADD_WIDTH 0x32 /* 32 */
+#define ETH_IPV4_SOURCE_ADD_WIDTH 0x20 /* 32 */
#define ETH_IPV4_SOURCE_ADD_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_IPV4_DESTINATION_ADD_ADDR 0x41036 /* 41036 */
-#define ETH_IPV4_DESTINATION_ADD_MASK 0x4294967295 /* 4294967295 */
+#define ETH_IPV4_DESTINATION_ADD_ADDR 0xa04c /* 41036 */
+#define ETH_IPV4_DESTINATION_ADD_MASK 0xffffffff /* 4294967295 */
#define ETH_IPV4_DESTINATION_ADD_OFFSET 0x0 /* 0 */
-#define ETH_IPV4_DESTINATION_ADD_WIDTH 0x32 /* 32 */
+#define ETH_IPV4_DESTINATION_ADD_WIDTH 0x20 /* 32 */
#define ETH_IPV4_DESTINATION_ADD_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define ETH_UDP_SOURCE_PORT_ADDR 0x41040 /* 41040 */
-#define ETH_UDP_SOURCE_PORT_MASK 0x65535 /* 65535 */
+#define ETH_UDP_SOURCE_PORT_ADDR 0xa050 /* 41040 */
+#define ETH_UDP_SOURCE_PORT_MASK 0xffff /* 65535 */
#define ETH_UDP_SOURCE_PORT_OFFSET 0x0 /* 0 */
-#define ETH_UDP_SOURCE_PORT_WIDTH 0x16 /* 16 */
-#define ETH_UDP_SOURCE_PORT_DEFAULT 0x32768 /* 32768 */
+#define ETH_UDP_SOURCE_PORT_WIDTH 0x10 /* 16 */
+#define ETH_UDP_SOURCE_PORT_DEFAULT 0x8000 /* 32768 */
/* Type = rw */
-#define ETH_UDP_DESTINATION_PORT_ADDR 0x41040 /* 41040 */
-#define ETH_UDP_DESTINATION_PORT_MASK 0x4294901760 /* 4294901760 */
-#define ETH_UDP_DESTINATION_PORT_OFFSET 0x16 /* 16 */
-#define ETH_UDP_DESTINATION_PORT_WIDTH 0x16 /* 16 */
-#define ETH_UDP_DESTINATION_PORT_DEFAULT 0x49152 /* 49152 */
+#define ETH_UDP_DESTINATION_PORT_ADDR 0xa050 /* 41040 */
+#define ETH_UDP_DESTINATION_PORT_MASK 0xffff0000 /* 4294901760 */
+#define ETH_UDP_DESTINATION_PORT_OFFSET 0x10 /* 16 */
+#define ETH_UDP_DESTINATION_PORT_WIDTH 0x10 /* 16 */
+#define ETH_UDP_DESTINATION_PORT_DEFAULT 0xc000 /* 49152 */
/* Type = rw */
-#define ETH_IPV6_V_ADDR 0x41088 /* 41088 */
-#define ETH_IPV6_V_MASK 0x15 /* 15 */
+#define ETH_IPV6_V_ADDR 0xa080 /* 41088 */
+#define ETH_IPV6_V_MASK 0xf /* 15 */
#define ETH_IPV6_V_OFFSET 0x0 /* 0 */
#define ETH_IPV6_V_WIDTH 0x4 /* 4 */
#define ETH_IPV6_V_DEFAULT 0x6 /* 6 */
/* Type = rw */
-#define ETH_IPV6_TRAFFIC_CLASS_ADDR 0x41092 /* 41092 */
-#define ETH_IPV6_TRAFFIC_CLASS_MASK 0x255 /* 255 */
+#define ETH_IPV6_TRAFFIC_CLASS_ADDR 0xa084 /* 41092 */
+#define ETH_IPV6_TRAFFIC_CLASS_MASK 0xff /* 255 */
#define ETH_IPV6_TRAFFIC_CLASS_OFFSET 0x0 /* 0 */
#define ETH_IPV6_TRAFFIC_CLASS_WIDTH 0x8 /* 8 */
#define ETH_IPV6_TRAFFIC_CLASS_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define ETH_IPV6_FLOW_LABEL_ADDR 0x41096 /* 41096 */
-#define ETH_IPV6_FLOW_LABEL_MASK 0x1048575 /* 1048575 */
+#define ETH_IPV6_FLOW_LABEL_ADDR 0xa088 /* 41096 */
+#define ETH_IPV6_FLOW_LABEL_MASK 0xfffff /* 1048575 */
#define ETH_IPV6_FLOW_LABEL_OFFSET 0x0 /* 0 */
-#define ETH_IPV6_FLOW_LABEL_WIDTH 0x20 /* 20 */
+#define ETH_IPV6_FLOW_LABEL_WIDTH 0x14 /* 20 */
#define ETH_IPV6_FLOW_LABEL_DEFAULT 0x0 /* 0 */
/* Type = rw */
-#define ETH_IPV6_NEXT_HEADER_ADDR 0x41100 /* 41100 */
-#define ETH_IPV6_NEXT_HEADER_MASK 0x255 /* 255 */
+#define ETH_IPV6_NEXT_HEADER_ADDR 0xa08c /* 41100 */
+#define ETH_IPV6_NEXT_HEADER_MASK 0xff /* 255 */
#define ETH_IPV6_NEXT_HEADER_OFFSET 0x0 /* 0 */
#define ETH_IPV6_NEXT_HEADER_WIDTH 0x8 /* 8 */
-#define ETH_IPV6_NEXT_HEADER_DEFAULT 0x17 /* 17 */
+#define ETH_IPV6_NEXT_HEADER_DEFAULT 0x11 /* 17 */
/* Type = rw */
-#define ETH_IPV6_HOP_LIMIT_ADDR 0x41104 /* 41104 */
-#define ETH_IPV6_HOP_LIMIT_MASK 0x255 /* 255 */
+#define ETH_IPV6_HOP_LIMIT_ADDR 0xa090 /* 41104 */
+#define ETH_IPV6_HOP_LIMIT_MASK 0xff /* 255 */
#define ETH_IPV6_HOP_LIMIT_OFFSET 0x0 /* 0 */
#define ETH_IPV6_HOP_LIMIT_WIDTH 0x8 /* 8 */
-#define ETH_IPV6_HOP_LIMIT_DEFAULT 0x64 /* 64 */
+#define ETH_IPV6_HOP_LIMIT_DEFAULT 0x40 /* 64 */
/* Type = rwpdef */
-#define ETH_IPV6_SOURCE_ADD_31_0_ADDR 0x41108 /* 41108 */
-#define ETH_IPV6_SOURCE_ADD_31_0_MASK 0x4294967295 /* 4294967295 */
+#define ETH_IPV6_SOURCE_ADD_31_0_ADDR 0xa094 /* 41108 */
+#define ETH_IPV6_SOURCE_ADD_31_0_MASK 0xffffffff /* 4294967295 */
#define ETH_IPV6_SOURCE_ADD_31_0_OFFSET 0x0 /* 0 */
-#define ETH_IPV6_SOURCE_ADD_31_0_WIDTH 0x32 /* 32 */
+#define ETH_IPV6_SOURCE_ADD_31_0_WIDTH 0x20 /* 32 */
#define ETH_IPV6_SOURCE_ADD_31_0_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_IPV6_SOURCE_ADD_63_32_ADDR 0x41112 /* 41112 */
-#define ETH_IPV6_SOURCE_ADD_63_32_MASK 0x4294967295 /* 4294967295 */
+#define ETH_IPV6_SOURCE_ADD_63_32_ADDR 0xa098 /* 41112 */
+#define ETH_IPV6_SOURCE_ADD_63_32_MASK 0xffffffff /* 4294967295 */
#define ETH_IPV6_SOURCE_ADD_63_32_OFFSET 0x0 /* 0 */
-#define ETH_IPV6_SOURCE_ADD_63_32_WIDTH 0x32 /* 32 */
+#define ETH_IPV6_SOURCE_ADD_63_32_WIDTH 0x20 /* 32 */
#define ETH_IPV6_SOURCE_ADD_63_32_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_IPV6_SOURCE_ADD_95_64_ADDR 0x41116 /* 41116 */
-#define ETH_IPV6_SOURCE_ADD_95_64_MASK 0x4294967295 /* 4294967295 */
+#define ETH_IPV6_SOURCE_ADD_95_64_ADDR 0xa09c /* 41116 */
+#define ETH_IPV6_SOURCE_ADD_95_64_MASK 0xffffffff /* 4294967295 */
#define ETH_IPV6_SOURCE_ADD_95_64_OFFSET 0x0 /* 0 */
-#define ETH_IPV6_SOURCE_ADD_95_64_WIDTH 0x32 /* 32 */
+#define ETH_IPV6_SOURCE_ADD_95_64_WIDTH 0x20 /* 32 */
#define ETH_IPV6_SOURCE_ADD_95_64_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_IPV6_SOURCE_ADD_127_96_ADDR 0x41120 /* 41120 */
-#define ETH_IPV6_SOURCE_ADD_127_96_MASK 0x4294967295 /* 4294967295 */
+#define ETH_IPV6_SOURCE_ADD_127_96_ADDR 0xa0a0 /* 41120 */
+#define ETH_IPV6_SOURCE_ADD_127_96_MASK 0xffffffff /* 4294967295 */
#define ETH_IPV6_SOURCE_ADD_127_96_OFFSET 0x0 /* 0 */
-#define ETH_IPV6_SOURCE_ADD_127_96_WIDTH 0x32 /* 32 */
+#define ETH_IPV6_SOURCE_ADD_127_96_WIDTH 0x20 /* 32 */
#define ETH_IPV6_SOURCE_ADD_127_96_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_IPV6_DESTINATION_ADD_31_0_ADDR 0x41124 /* 41124 */
-#define ETH_IPV6_DESTINATION_ADD_31_0_MASK 0x4294967295 /* 4294967295 */
+#define ETH_IPV6_DESTINATION_ADD_31_0_ADDR 0xa0a4 /* 41124 */
+#define ETH_IPV6_DESTINATION_ADD_31_0_MASK 0xffffffff /* 4294967295 */
#define ETH_IPV6_DESTINATION_ADD_31_0_OFFSET 0x0 /* 0 */
-#define ETH_IPV6_DESTINATION_ADD_31_0_WIDTH 0x32 /* 32 */
+#define ETH_IPV6_DESTINATION_ADD_31_0_WIDTH 0x20 /* 32 */
#define ETH_IPV6_DESTINATION_ADD_31_0_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_IPV6_DESTINATION_ADD_63_32_ADDR 0x41128 /* 41128 */
-#define ETH_IPV6_DESTINATION_ADD_63_32_MASK 0x4294967295 /* 4294967295 */
+#define ETH_IPV6_DESTINATION_ADD_63_32_ADDR 0xa0a8 /* 41128 */
+#define ETH_IPV6_DESTINATION_ADD_63_32_MASK 0xffffffff /* 4294967295 */
#define ETH_IPV6_DESTINATION_ADD_63_32_OFFSET 0x0 /* 0 */
-#define ETH_IPV6_DESTINATION_ADD_63_32_WIDTH 0x32 /* 32 */
+#define ETH_IPV6_DESTINATION_ADD_63_32_WIDTH 0x20 /* 32 */
#define ETH_IPV6_DESTINATION_ADD_63_32_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_IPV6_DESTINATION_ADD_95_64_ADDR 0x41132 /* 41132 */
-#define ETH_IPV6_DESTINATION_ADD_95_64_MASK 0x4294967295 /* 4294967295 */
+#define ETH_IPV6_DESTINATION_ADD_95_64_ADDR 0xa0ac /* 41132 */
+#define ETH_IPV6_DESTINATION_ADD_95_64_MASK 0xffffffff /* 4294967295 */
#define ETH_IPV6_DESTINATION_ADD_95_64_OFFSET 0x0 /* 0 */
-#define ETH_IPV6_DESTINATION_ADD_95_64_WIDTH 0x32 /* 32 */
+#define ETH_IPV6_DESTINATION_ADD_95_64_WIDTH 0x20 /* 32 */
#define ETH_IPV6_DESTINATION_ADD_95_64_DEFAULT 0x0 /* 0 */
/* Type = rwpdef */
-#define ETH_IPV6_DESTINATION_ADD_127_96_ADDR 0x41136 /* 41136 */
-#define ETH_IPV6_DESTINATION_ADD_127_96_MASK 0x4294967295 /* 4294967295 */
+#define ETH_IPV6_DESTINATION_ADD_127_96_ADDR 0xa0b0 /* 41136 */
+#define ETH_IPV6_DESTINATION_ADD_127_96_MASK 0xffffffff /* 4294967295 */
#define ETH_IPV6_DESTINATION_ADD_127_96_OFFSET 0x0 /* 0 */
-#define ETH_IPV6_DESTINATION_ADD_127_96_WIDTH 0x32 /* 32 */
+#define ETH_IPV6_DESTINATION_ADD_127_96_WIDTH 0x20 /* 32 */
#define ETH_IPV6_DESTINATION_ADD_127_96_DEFAULT 0x0 /* 0 */
/*-----------------------------------------------------------------------------
* C Header bank register definitions for bank roe_framer_v1_0_stats
* with prefix stats_ @ address 0xc000
- *-----------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
*/
/* Type = roSig */
-#define STATS_TOTAL_RX_GOOD_PKT_CNT_ADDR 0x49152 /* 49152 */
-#define STATS_TOTAL_RX_GOOD_PKT_CNT_MASK 0x4294967295 /* 4294967295 */
+#define STATS_TOTAL_RX_GOOD_PKT_CNT_ADDR 0xc000 /* 49152 */
+#define STATS_TOTAL_RX_GOOD_PKT_CNT_MASK 0xffffffff /* 4294967295 */
#define STATS_TOTAL_RX_GOOD_PKT_CNT_OFFSET 0x0 /* 0 */
-#define STATS_TOTAL_RX_GOOD_PKT_CNT_WIDTH 0x32 /* 32 */
+#define STATS_TOTAL_RX_GOOD_PKT_CNT_WIDTH 0x20 /* 32 */
#define STATS_TOTAL_RX_GOOD_PKT_CNT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_TOTAL_RX_BAD_PKT_CNT_ADDR 0x49156 /* 49156 */
-#define STATS_TOTAL_RX_BAD_PKT_CNT_MASK 0x4294967295 /* 4294967295 */
+#define STATS_TOTAL_RX_BAD_PKT_CNT_ADDR 0xc004 /* 49156 */
+#define STATS_TOTAL_RX_BAD_PKT_CNT_MASK 0xffffffff /* 4294967295 */
#define STATS_TOTAL_RX_BAD_PKT_CNT_OFFSET 0x0 /* 0 */
-#define STATS_TOTAL_RX_BAD_PKT_CNT_WIDTH 0x32 /* 32 */
+#define STATS_TOTAL_RX_BAD_PKT_CNT_WIDTH 0x20 /* 32 */
#define STATS_TOTAL_RX_BAD_PKT_CNT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_TOTAL_RX_BAD_FCS_CNT_ADDR 0x49160 /* 49160 */
-#define STATS_TOTAL_RX_BAD_FCS_CNT_MASK 0x4294967295 /* 4294967295 */
+#define STATS_TOTAL_RX_BAD_FCS_CNT_ADDR 0xc008 /* 49160 */
+#define STATS_TOTAL_RX_BAD_FCS_CNT_MASK 0xffffffff /* 4294967295 */
#define STATS_TOTAL_RX_BAD_FCS_CNT_OFFSET 0x0 /* 0 */
-#define STATS_TOTAL_RX_BAD_FCS_CNT_WIDTH 0x32 /* 32 */
+#define STATS_TOTAL_RX_BAD_FCS_CNT_WIDTH 0x20 /* 32 */
#define STATS_TOTAL_RX_BAD_FCS_CNT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_USER_DATA_RX_PACKETS_CNT_ADDR 0x49164 /* 49164 */
-#define STATS_USER_DATA_RX_PACKETS_CNT_MASK 0x4294967295 /* 4294967295 */
+#define STATS_USER_DATA_RX_PACKETS_CNT_ADDR 0xc00c /* 49164 */
+#define STATS_USER_DATA_RX_PACKETS_CNT_MASK 0xffffffff /* 4294967295 */
#define STATS_USER_DATA_RX_PACKETS_CNT_OFFSET 0x0 /* 0 */
-#define STATS_USER_DATA_RX_PACKETS_CNT_WIDTH 0x32 /* 32 */
+#define STATS_USER_DATA_RX_PACKETS_CNT_WIDTH 0x20 /* 32 */
#define STATS_USER_DATA_RX_PACKETS_CNT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_USER_DATA_RX_GOOD_PKT_CNT_ADDR 0x49168 /* 49168 */
-#define STATS_USER_DATA_RX_GOOD_PKT_CNT_MASK 0x4294967295 /* 4294967295 */
+#define STATS_USER_DATA_RX_GOOD_PKT_CNT_ADDR 0xc010 /* 49168 */
+#define STATS_USER_DATA_RX_GOOD_PKT_CNT_MASK 0xffffffff /* 4294967295 */
#define STATS_USER_DATA_RX_GOOD_PKT_CNT_OFFSET 0x0 /* 0 */
-#define STATS_USER_DATA_RX_GOOD_PKT_CNT_WIDTH 0x32 /* 32 */
+#define STATS_USER_DATA_RX_GOOD_PKT_CNT_WIDTH 0x20 /* 32 */
#define STATS_USER_DATA_RX_GOOD_PKT_CNT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_USER_DATA_RX_BAD_PKT_CNT_ADDR 0x49172 /* 49172 */
-#define STATS_USER_DATA_RX_BAD_PKT_CNT_MASK 0x4294967295 /* 4294967295 */
+#define STATS_USER_DATA_RX_BAD_PKT_CNT_ADDR 0xc014 /* 49172 */
+#define STATS_USER_DATA_RX_BAD_PKT_CNT_MASK 0xffffffff /* 4294967295 */
#define STATS_USER_DATA_RX_BAD_PKT_CNT_OFFSET 0x0 /* 0 */
-#define STATS_USER_DATA_RX_BAD_PKT_CNT_WIDTH 0x32 /* 32 */
+#define STATS_USER_DATA_RX_BAD_PKT_CNT_WIDTH 0x20 /* 32 */
#define STATS_USER_DATA_RX_BAD_PKT_CNT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_USER_DATA_RX_BAD_FCS_CNT_ADDR 0x49176 /* 49176 */
-#define STATS_USER_DATA_RX_BAD_FCS_CNT_MASK 0x4294967295 /* 4294967295 */
+#define STATS_USER_DATA_RX_BAD_FCS_CNT_ADDR 0xc018 /* 49176 */
+#define STATS_USER_DATA_RX_BAD_FCS_CNT_MASK 0xffffffff /* 4294967295 */
#define STATS_USER_DATA_RX_BAD_FCS_CNT_OFFSET 0x0 /* 0 */
-#define STATS_USER_DATA_RX_BAD_FCS_CNT_WIDTH 0x32 /* 32 */
+#define STATS_USER_DATA_RX_BAD_FCS_CNT_WIDTH 0x20 /* 32 */
#define STATS_USER_DATA_RX_BAD_FCS_CNT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_USER_CTRL_RX_PACKETS_CNT_ADDR 0x49180 /* 49180 */
-#define STATS_USER_CTRL_RX_PACKETS_CNT_MASK 0x4294967295 /* 4294967295 */
+#define STATS_USER_CTRL_RX_PACKETS_CNT_ADDR 0xc01c /* 49180 */
+#define STATS_USER_CTRL_RX_PACKETS_CNT_MASK 0xffffffff /* 4294967295 */
#define STATS_USER_CTRL_RX_PACKETS_CNT_OFFSET 0x0 /* 0 */
-#define STATS_USER_CTRL_RX_PACKETS_CNT_WIDTH 0x32 /* 32 */
+#define STATS_USER_CTRL_RX_PACKETS_CNT_WIDTH 0x20 /* 32 */
#define STATS_USER_CTRL_RX_PACKETS_CNT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_USER_CTRL_RX_GOOD_PKT_CNT_ADDR 0x49184 /* 49184 */
-#define STATS_USER_CTRL_RX_GOOD_PKT_CNT_MASK 0x4294967295 /* 4294967295 */
+#define STATS_USER_CTRL_RX_GOOD_PKT_CNT_ADDR 0xc020 /* 49184 */
+#define STATS_USER_CTRL_RX_GOOD_PKT_CNT_MASK 0xffffffff /* 4294967295 */
#define STATS_USER_CTRL_RX_GOOD_PKT_CNT_OFFSET 0x0 /* 0 */
-#define STATS_USER_CTRL_RX_GOOD_PKT_CNT_WIDTH 0x32 /* 32 */
+#define STATS_USER_CTRL_RX_GOOD_PKT_CNT_WIDTH 0x20 /* 32 */
#define STATS_USER_CTRL_RX_GOOD_PKT_CNT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_USER_CTRL_RX_BAD_PKT_CNT_ADDR 0x49188 /* 49188 */
-#define STATS_USER_CTRL_RX_BAD_PKT_CNT_MASK 0x4294967295 /* 4294967295 */
+#define STATS_USER_CTRL_RX_BAD_PKT_CNT_ADDR 0xc024 /* 49188 */
+#define STATS_USER_CTRL_RX_BAD_PKT_CNT_MASK 0xffffffff /* 4294967295 */
#define STATS_USER_CTRL_RX_BAD_PKT_CNT_OFFSET 0x0 /* 0 */
-#define STATS_USER_CTRL_RX_BAD_PKT_CNT_WIDTH 0x32 /* 32 */
+#define STATS_USER_CTRL_RX_BAD_PKT_CNT_WIDTH 0x20 /* 32 */
#define STATS_USER_CTRL_RX_BAD_PKT_CNT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_USER_CTRL_RX_BAD_FCS_CNT_ADDR 0x49192 /* 49192 */
-#define STATS_USER_CTRL_RX_BAD_FCS_CNT_MASK 0x4294967295 /* 4294967295 */
+#define STATS_USER_CTRL_RX_BAD_FCS_CNT_ADDR 0xc028 /* 49192 */
+#define STATS_USER_CTRL_RX_BAD_FCS_CNT_MASK 0xffffffff /* 4294967295 */
#define STATS_USER_CTRL_RX_BAD_FCS_CNT_OFFSET 0x0 /* 0 */
-#define STATS_USER_CTRL_RX_BAD_FCS_CNT_WIDTH 0x32 /* 32 */
+#define STATS_USER_CTRL_RX_BAD_FCS_CNT_WIDTH 0x20 /* 32 */
#define STATS_USER_CTRL_RX_BAD_FCS_CNT_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_USER_DATA_RX_PKTS_RATE_ADDR 0x49196 /* 49196 */
-#define STATS_USER_DATA_RX_PKTS_RATE_MASK 0x4294967295 /* 4294967295 */
+#define STATS_USER_DATA_RX_PKTS_RATE_ADDR 0xc02c /* 49196 */
+#define STATS_USER_DATA_RX_PKTS_RATE_MASK 0xffffffff /* 4294967295 */
#define STATS_USER_DATA_RX_PKTS_RATE_OFFSET 0x0 /* 0 */
-#define STATS_USER_DATA_RX_PKTS_RATE_WIDTH 0x32 /* 32 */
+#define STATS_USER_DATA_RX_PKTS_RATE_WIDTH 0x20 /* 32 */
#define STATS_USER_DATA_RX_PKTS_RATE_DEFAULT 0x0 /* 0 */
/* Type = roSig */
-#define STATS_USER_CTRL_RX_PKTS_RATE_ADDR 0x49200 /* 49200 */
-#define STATS_USER_CTRL_RX_PKTS_RATE_MASK 0x4294967295 /* 4294967295 */
+#define STATS_USER_CTRL_RX_PKTS_RATE_ADDR 0xc030 /* 49200 */
+#define STATS_USER_CTRL_RX_PKTS_RATE_MASK 0xffffffff /* 4294967295 */
#define STATS_USER_CTRL_RX_PKTS_RATE_OFFSET 0x0 /* 0 */
-#define STATS_USER_CTRL_RX_PKTS_RATE_WIDTH 0x32 /* 32 */
+#define STATS_USER_CTRL_RX_PKTS_RATE_WIDTH 0x20 /* 32 */
#define STATS_USER_CTRL_RX_PKTS_RATE_DEFAULT 0x0 /* 0 */
projects / zynq / linux.git / commitdiff