dt-bindings: display: xlnx: Adding dsi bindings

Adding device tree documentation of dsi.
The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem
implements the Mobile Industry Processor Interface (MIPI) based display
interface. The Display Serial Interface Specification defines protocols
between a host processor and peripheral devices using a D-PHY physical
interface. The DSI specification builds on existing specifications by
adopting pixel formats and command set defined in MIPI Alliance
specifications for Display Pixel Interface 2 (DPI-2) and Display
Command Set (DCS)

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt
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+Device-Tree bindings for Xilinx MIPI DSI Tx IP core
+
+The IP core supports transmission of video data in MIPI DSI protocol.
+
+Required properties:
+ - compatible: Should be "xlnx,dsi".
+
+ - reg: Base address and size of the IP core.
+
+ - xlnx,dsi-datatype: Color format. The value should be one of "MIPI_DSI_FMT_RGB888",
+  "MIPI_DSI_FMT_RGB666", "MIPI_DSI_FMT_RGB666_PACKED" or "MIPI_DSI_FMT_RGB565".
+
+ - simple_panel: The subnode for connected panel. This represents the
+   DSI peripheral connected to the DSI host node. Please refer to
+   Documentation/devicetree/bindings/display/mipi-dsi-bus.txt. The
+   simple-panel driver has auo,b101uan01 panel timing parameters added along
+   with other existing panels. DSI driver derive the required Tx IP controller
+   timing values from the panel timing parameters.
+
+ - port: Logical block can be used / connected independently with
+   external device. In the display controller port nodes, topology
+   for entire pipeline should be described using the DT bindings defined in
+   Documentation/devicetree/bindings/graph.txt.
+
+ - xlnx,dsi-num-lanes: Possible number of DSI lanes for the Tx controller.
+   The values should be 1, 2, 3 or 4. Based on xlnx,dsi-num-lanes and
+   line rate for the MIPI D-PHY core in Mbps, the AXI4-stream received by
+   Xilinx MIPI DSI Tx IP core adds markers as per DSI protocol and the packet
+   thus framed is convered to serial data by MIPI D-PHY core. Please refer
+   Xilinx pg238 for more details. This value should be equal to the number
+   of lanes supported by the connected DSI panel. Panel has to support this
+   value or has to be programmed to the same value that DSI Tx controller is
+   configured to.
+
+Required simple_panel properties:
+ - compatible: Value should be one of the panel names in
+   Documentation/devicetree/bindings/display/panel/. e.g. "auo,b101uan01".
+   For available panel compatible strings, please refer to bindings in
+   Documentation/devicetree/bindings/display/panel/
+
+Example:
+
+#include <dt-bindings/drm/mipi-dsi.h>
+       mipi_dsi_tx_subsystem@80000000 {
+               compatible = "xlnx,dsi";
+               reg = <0x0 0x80000000 0x0 0x10000>;
+               xlnx,dsi-num-lanes = <4>;
+               xlnx,dsi-data-type = <MIPI_DSI_FMT_RGB888>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               encoder_dsi_port: port@0 {
+                       reg = <0>;
+                       dsi_encoder: endpoint {
+                               remote-endpoint = <&xyz_port>;
+                       };
+               };
+               simple_panel: simple-panel@0 {
+                       compatible = "auo,b101uan01";
+                       reg = <0>;
+                       };
+               };