arm64: zynqmp: devicetree: Update GEM0/1/2 clocks

- pclk should be lpd_lsbus; correct the same
- Add rx_clk
- Reorder for readability

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index c5e8f533a18f03cb46d524fa28e711bcd2690841..b2ef4e3aefb95574d343afc051edabb75b16ded7 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -190,18 +190,18 @@
 };
 
 &gem0 {
-       clocks = <&clkc 45>, <&clkc 45>, <&clkc 49>;
-       clock-names = "pclk", "tx_clk", "hclk";
+       clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>;
+       clock-names = "pclk", "hclk", "tx_clk", "rx_clk";
 };
 
 &gem1 {
-       clocks = <&clkc 46>, <&clkc 46>, <&clkc 50>;
-       clock-names = "pclk", "tx_clk", "hclk";
+       clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>;
+       clock-names = "pclk", "hclk", "tx_clk", "rx_clk";
 };
 
 &gem2 {
-       clocks = <&clkc 47>, <&clkc 47>, <&clkc 51>;
-       clock-names = "pclk", "tx_clk", "hclk";
+       clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>;
+       clock-names = "pclk", "hclk", "tx_clk", "rx_clk";
 };
 
 &gem3 {