dt-bindings: net: xilinx_axienet: Add DMA address width property

The AXIDMA and MCDMA IP support configurable address width. To enable
programming dma related masks add an optional "xlnx,addrwidth" property.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Reviewed-by: Harini Katakam <harini.katakam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
index 01e2b11176a8777ac5e9b049787ff1aaaf4a31e6..d5d5c3bbc90bc58759b0e1f48c63e21317671edb 100644 (file)
--- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
+++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
@@ -59,6 +59,9 @@ Optional properties (When AxiEthernet is configured with MCDMA):
 Optional properties (When USXGMII is in use):
 - xlnx,usxgmii-rate    : USXGMII PHY speed - can be 10, 100, 1000, 2500,
                          5000 or 10000.
+Optional properties for connected DMA node:
+- xlnx,addrwidth       : Specify the width of the DMA address space in bits.
+                         Valid range is 32-64. Default is 32.
 
 NOTE: Time Sensitive Networking (TSN) related DT bindings are explained in [4].