zynq: slcr: Rename xslcr to zynq_slcr

zynq specific functions should use zynq_ prefix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 98ce038bc1c0dfb9267871282304112960528945..4e27dec0df93e78534cb3f43d1947b6e15af49cb 100644 (file)
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -32,11 +32,11 @@ extern int zynq_cpun_start(u32 address, int cpu);
 extern struct smp_operations zynq_smp_ops __initdata;
 #endif
 
-extern void xslcr_write(u32 val, u32 offset);
-extern u32 xslcr_read(u32 offset);
+extern void zynq_slcr_write(u32 val, u32 offset);
+extern u32 zynq_slcr_read(u32 offset);
 
-extern void xslcr_init_preload_fpga(void);
-extern void xslcr_init_postload_fpga(void);
+extern void zynq_slcr_init_preload_fpga(void);
+extern void zynq_slcr_init_postload_fpga(void);
 
 extern void __iomem *zynq_slcr_base;
 extern void __iomem *zynq_scu_base;

diff --git a/arch/arm/mach-zynq/pm.c b/arch/arm/mach-zynq/pm.c
index 847a6aba822be155384295f0d7515fa2c80d09ed..84f1a2629507a55923b0e168068b2282373eb32f 100644 (file)
--- a/arch/arm/mach-zynq/pm.c
+++ b/arch/arm/mach-zynq/pm.c
@@ -91,9 +91,9 @@ static int zynq_pm_suspend(unsigned long arg)
        }
 
        /* Topswitch clock stop disable */
-       reg = xslcr_read(SLCR_TOPSW_CLK_CTRL);
+       reg = zynq_slcr_read(SLCR_TOPSW_CLK_CTRL);
        reg |= TOPSW_CLK_CTRL_DIS_MASK;
-       xslcr_write(reg, SLCR_TOPSW_CLK_CTRL);
+       zynq_slcr_write(reg, SLCR_TOPSW_CLK_CTRL);
 
        /* A9 clock gating */
        asm volatile ("mrc  p15, 0, r12, c15, c0, 0\n"
@@ -147,9 +147,9 @@ static int zynq_pm_suspend(unsigned long arg)
        }
 
        /* Topswitch clock stop disable */
-       reg = xslcr_read(SLCR_TOPSW_CLK_CTRL);
+       reg = zynq_slcr_read(SLCR_TOPSW_CLK_CTRL);
        reg &= ~TOPSW_CLK_CTRL_DIS_MASK;
-       xslcr_write(reg, SLCR_TOPSW_CLK_CTRL);
+       zynq_slcr_write(reg, SLCR_TOPSW_CLK_CTRL);
 
        /* SCU standby mode */
        if (zynq_scu_base) {

diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 9313125a0f17c891981bb22addb1e566b01c8404..8ee0ed23cdcf2db50fefad7f00f8381fa0f1b5f4 100644 (file)
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -63,60 +63,60 @@ void zynq_slcr_system_reset(void)
 }
 
 /**
- * xslcr_write - Write to a register in SLCR block
+ * zynq_slcr_write - Write to a register in SLCR block
  *
  * @offset:    Register offset in SLCR block
  * @val:       Value to write to the register
  **/
-void xslcr_write(u32 val, u32 offset)
+void zynq_slcr_write(u32 val, u32 offset)
 {
        writel(val, zynq_slcr_base + offset);
 }
-EXPORT_SYMBOL(xslcr_write);
+EXPORT_SYMBOL(zynq_slcr_write);
 
 /**
- * xslcr_read - Read a register in SLCR block
+ * zynq_slcr_read - Read a register in SLCR block
  *
  * @offset:    Register offset in SLCR block
  *
  * return:     Value read from the SLCR register
  **/
-u32 xslcr_read(u32 offset)
+u32 zynq_slcr_read(u32 offset)
 {
        return readl(zynq_slcr_base + offset);
 }
-EXPORT_SYMBOL(xslcr_read);
+EXPORT_SYMBOL(zynq_slcr_read);
 
 /**
- * xslcr_init_preload_fpga - Disable communication from the PL to PS.
+ * zynq_slcr_init_preload_fpga - Disable communication from the PL to PS.
  */
-void xslcr_init_preload_fpga(void)
+void zynq_slcr_init_preload_fpga(void)
 {
 
        /* Assert FPGA top level output resets */
-       xslcr_write(0xF, SLCR_FPGA_RST_CTRL_OFFSET);
+       zynq_slcr_write(0xF, SLCR_FPGA_RST_CTRL_OFFSET);
 
        /* Disable level shifters */
-       xslcr_write(0, SLCR_LVL_SHFTR_EN_OFFSET);
+       zynq_slcr_write(0, SLCR_LVL_SHFTR_EN_OFFSET);
 
        /* Enable output level shifters */
-       xslcr_write(0xA, SLCR_LVL_SHFTR_EN_OFFSET);
+       zynq_slcr_write(0xA, SLCR_LVL_SHFTR_EN_OFFSET);
 }
-EXPORT_SYMBOL(xslcr_init_preload_fpga);
+EXPORT_SYMBOL(zynq_slcr_init_preload_fpga);
 
 /**
- * xslcr_init_postload_fpga - Re-enable communication from the PL to PS.
+ * zynq_slcr_init_postload_fpga - Re-enable communication from the PL to PS.
  */
-void xslcr_init_postload_fpga(void)
+void zynq_slcr_init_postload_fpga(void)
 {
 
        /* Enable level shifters */
-       xslcr_write(0xf, SLCR_LVL_SHFTR_EN_OFFSET);
+       zynq_slcr_write(0xf, SLCR_LVL_SHFTR_EN_OFFSET);
 
        /* Deassert AXI interface resets */
-       xslcr_write(0, SLCR_FPGA_RST_CTRL_OFFSET);
+       zynq_slcr_write(0, SLCR_FPGA_RST_CTRL_OFFSET);
 }
-EXPORT_SYMBOL(xslcr_init_postload_fpga);
+EXPORT_SYMBOL(zynq_slcr_init_postload_fpga);
 
 /**
  * zynq_slcr_cpu_start - Start cpu

diff --git a/drivers/char/xilinx_devcfg.c b/drivers/char/xilinx_devcfg.c
index 97ed727faa483c427d05c2cd1cd1c86291bc9131..ebd701daa0d98ba471493fb319cfbd090c51410f 100644 (file)
--- a/drivers/char/xilinx_devcfg.c
+++ b/drivers/char/xilinx_devcfg.c
@@ -33,8 +33,8 @@
 #include <linux/types.h>
 #include <linux/uaccess.h>
 
-extern void xslcr_init_preload_fpga(void);
-extern void xslcr_init_postload_fpga(void);
+extern void zynq_slcr_init_preload_fpga(void);
+extern void zynq_slcr_init_postload_fpga(void);
 
 #define DRIVER_NAME "xdevcfg"
 #define XDEVCFG_DEVICES 1
@@ -512,11 +512,11 @@ static int xdevcfg_open(struct inode *inode, struct file *file)
 
        /*
         * If is_partial_bitstream is set, then PROG_B is not asserted
-        * (xdevcfg_reset_pl function) and also xslcr_init_preload_fpga and
-        * xslcr_init_postload_fpga functions are not invoked.
+        * (xdevcfg_reset_pl function) and also zynq_slcr_init_preload_fpga and
+        * zynq_slcr_init_postload_fpga functions are not invoked.
         */
        if (!drvdata->is_partial_bitstream)
-               xslcr_init_preload_fpga();
+               zynq_slcr_init_preload_fpga();
 
        /*
         * Only do the reset of the PL for Zynq as it causes problems on the
@@ -549,7 +549,7 @@ static int xdevcfg_release(struct inode *inode, struct file *file)
        struct xdevcfg_drvdata *drvdata = file->private_data;
 
        if (!drvdata->is_partial_bitstream)
-               xslcr_init_postload_fpga();
+               zynq_slcr_init_postload_fpga();
 
        if (drvdata->residue_len)
                printk("Did not transfer last %d bytes\n",
@@ -1512,7 +1512,7 @@ static DEVICE_ATTR(prog_done, 0644, xdevcfg_show_prog_done_status,
  * xdevcfg_set_is_partial_bitstream() - This function sets the
  * is_partial_bitstream variable. If is_partial_bitstream is set,
  * then PROG_B is not asserted (xdevcfg_reset_pl) and also
- * xslcr_init_preload_fpga and xslcr_init_postload_fpga functions
+ * zynq_slcr_init_preload_fpga and zynq_slcr_init_postload_fpga functions
  * are not invoked.
  * @dev:       Pointer to the device structure.
  * @attr:      Pointer to the device attribute structure.