This patch fixes the below issues
--> when hardware is idle we need to toggle the SG bit
inorder to update new value to the current descriptor
register other wise undefined results will occur.
--> Halt bit is not valid for cdma case add checks
for the same.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
+ dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
+ XILINX_CDMA_CR_SGMODE);
+
+ dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
+ XILINX_CDMA_CR_SGMODE);
+
xilinx_write(chan, XILINX_DMA_REG_CURDESC,
head_desc->async_tx.phys);
xilinx_write(chan, XILINX_DMA_REG_CURDESC,
head_desc->async_tx.phys);
if (chan->cyclic)
xilinx_dma_chan_reset(chan);
if (chan->cyclic)
xilinx_dma_chan_reset(chan);
- /* Halt the DMA engine */
- xilinx_dma_halt(chan);
+ if (!(chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) {
+ /* Halt the DMA engine */
+ xilinx_dma_halt(chan);
+ }
/* Remove and free all of the descriptors in the lists */
xilinx_dma_free_descriptors(chan);
/* Remove and free all of the descriptors in the lists */
xilinx_dma_free_descriptors(chan);
+ if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
+ dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
+ XILINX_CDMA_CR_SGMODE);
+