dt-bindings: zynqmp: nvmem: Aling dt binding with mainline

Mainline binding was approved that's why aligned with internal one.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
index 23af8663364d6137ac25e97469cdd217459182ea..be126ccf480205ea81019fde9098fe88679df576 100644 (file)
--- a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
+++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
@@ -1,4 +1,8 @@
+--------------------------------------------------------------------------
 =  Zynq UltraScale+ MPSoC nvmem firmware driver binding =
+--------------------------------------------------------------------------
+The nvmem_firmware node provides access to the hardware related data
+like soc revision, IDCODE... etc, By using the firmware interface.
 
 Required properties:
 - compatible: should be "xlnx,zynqmp-nvmem-fw"
@@ -7,97 +11,107 @@ Required properties:
 Are child nodes of silicon id, bindings of which as described in
 bindings/nvmem/nvmem.txt
 
-Example:
+-------
+ Example
+-------
+firmware {
+       zynqmp_firmware: zynqmp-firmware {
+               compatible = "xlnx,zynqmp-firmware";
+               method = "smc";
 
-       nvmem_firmware {
-               compatible = "xlnx,zynqmp-nvmem-fw";
-               #address-cells = <1>;
-               #size-cells = <1>;
+               nvmem_firmware {
+                       compatible = "xlnx,zynqmp-nvmem-fw";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
 
-                /* Data cells */
-               soc_revision: soc_revision@0 {
-                       reg = <0x0 0x4>;
-               };
-               /*
-                * efuse memory access:
-                * all the efuse feilds need to be read
-                * with the exact size specified in the node
-                */
-               /* DNA */
-               efuse_dna: efuse_dna@c {
-                       reg = <0xc 0xc>;
-               };
-               /* User 0 */
-               efuse_usr0: efuse_usr0@20 {
-                       reg = <0x20 0x4>;
-               };
-               /* User 1 */
-               efuse_usr1: efuse_usr1@24 {
-                       reg = <0x24 0x4>;
-               };
-               /* User 2 */
-               efuse_usr2: efuse_usr2@28 {
-                       reg = <0x28 0x4>;
-               };
-               /* User 3 */
-               efuse_usr3: efuse_usr3@2c {
-                       reg = <0x2c 0x4>;
-               };
-               /* User 4 */
-               efuse_usr4: efuse_usr4@30 {
-                       reg = <0x30 0x4>;
-               };
-               /* User 5 */
-               efuse_usr5: efuse_usr5@34 {
-                       reg = <0x34 0x4>;
-               };
-               /* User 6 */
-               efuse_usr6: efuse_usr6@38 {
-                       reg = <0x38 0x4>;
-               };
-               /* User 7 */
-               efuse_usr7: efuse_usr7@3c {
-                       reg = <0x3c 0x4>;
-               };
-               /* Misc user control bits */
-               efuse_miscusr: efuse_miscusr@40 {
-                       reg = <0x40 0x4>;
-               };
-               /* PUF chash */
-               efuse_chash: efuse_chash@50 {
-                       reg = <0x50 0x4>;
-               };
-               /* PUF misc */
-               efuse_pufmisc: efuse_pufmisc@54 {
-                       reg = <0x54 0x4>;
-               };
-               /* SEC_CTRL */
-               efuse_sec: efuse_sec@58 {
-                       reg = <0x58 0x4>;
-               };
-               /* SPK ID */
-               efuse_spkid: efuse_spkid@5c {
-                       reg = <0x5c 0x4>;
-               };
-               /* PPK0 hash */
-               efuse_ppk0hash: efuse_ppk0hash@a0 {
-                       reg = <0xa0 0x30>;
-               };
-               /* PPK1 hash */
-               efuse_ppk1hash: efuse_ppk1hash@d0 {
-                       reg = <0xd0 0x30>;
+                       /* Data cells */
+                       soc_revision: soc_revision@0 {
+                               reg = <0x0 0x4>;
+                       };
+                       /*
+                       * efuse memory access:
+                       * all the efuse feilds need to be read
+                       * with the exact size specified in the node
+                       */
+                       /* DNA */
+                       efuse_dna: efuse_dna@c {
+                               reg = <0xc 0xc>;
+                       };
+                       /* User 0 */
+                       efuse_usr0: efuse_usr0@20 {
+                               reg = <0x20 0x4>;
+                       };
+                       /* User 1 */
+                       efuse_usr1: efuse_usr1@24 {
+                               reg = <0x24 0x4>;
+                       };
+                       /* User 2 */
+                       efuse_usr2: efuse_usr2@28 {
+                               reg = <0x28 0x4>;
+                       };
+                       /* User 3 */
+                       efuse_usr3: efuse_usr3@2c {
+                               reg = <0x2c 0x4>;
+                       };
+                       /* User 4 */
+                       efuse_usr4: efuse_usr4@30 {
+                               reg = <0x30 0x4>;
+                       };
+                       /* User 5 */
+                       efuse_usr5: efuse_usr5@34 {
+                               reg = <0x34 0x4>;
+                       };
+                       /* User 6 */
+                       efuse_usr6: efuse_usr6@38 {
+                               reg = <0x38 0x4>;
+                       };
+                       /* User 7 */
+                       efuse_usr7: efuse_usr7@3c {
+                               reg = <0x3c 0x4>;
+                       };
+                       /* Misc user control bits */
+                       efuse_miscusr: efuse_miscusr@40 {
+                               reg = <0x40 0x4>;
+                       };
+                       /* PUF chash */
+                       efuse_chash: efuse_chash@50 {
+                               reg = <0x50 0x4>;
+                       };
+                       /* PUF misc */
+                       efuse_pufmisc: efuse_pufmisc@54 {
+                               reg = <0x54 0x4>;
+                       };
+                       /* SEC_CTRL */
+                       efuse_sec: efuse_sec@58 {
+                               reg = <0x58 0x4>;
+                       };
+                       /* SPK ID */
+                       efuse_spkid: efuse_spkid@5c {
+                               reg = <0x5c 0x4>;
+                       };
+                       /* PPK0 hash */
+                       efuse_ppk0hash: efuse_ppk0hash@a0 {
+                               reg = <0xa0 0x30>;
+                       };
+                       /* PPK1 hash */
+                       efuse_ppk1hash: efuse_ppk1hash@d0 {
+                               reg = <0xd0 0x30>;
+                       };
                };
        };
+};
 
 = Data consumers =
 Are device nodes which consume nvmem data cells.
 
 For example:
-
        pcap {
                ...
+
                nvmem-cells = <&soc_revision>;
                nvmem-cell-names = "soc_revision";
+
+               ...
        };
 
 To program efuse memory, one should request specified bytes of size as below,