Documentation: devicetree: axienet: Add clock support

This patch updates binding doc with
clock properties.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
index 6cadba60a1ce5b5bcb3d1bf98f4f2ac117d3eb55..672b97e740c71a7c937745dc146ee773a64c9abd 100644 (file)
--- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
+++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
@@ -27,6 +27,8 @@ Optional properties:
 - xlnx,eth-hasnobuf    : Used when 1G MAC is configured in non processor mode.
 - xlnx,rxtsfifo        : Configures the axi fifo for receive timestamping.
 - xlnx,include-dre     : Tells whether DMA h/w is configured with DRE or not.
+- clocks               : Input clock specifier. Refer to common clock bindings.
+- clock-names          : Input clock name, should be ethernet_clk and dma_clk.
 
 Example: