xilinx: v4l: m2m: Set default mode for framebuffer IP

- Set the framebuffer IP to default mode instead of auto-restart
  mode for mem2mem usecases due to reason explained below:

- By framebuffer IP is programmed by driver to use a special mode
  called auto_restart mode or free-running mode in which core processes
  data periodically irrespective of input rate.

- So in this scenario, if input is stalled for sometime,
  then framebuffer IP will still process with previous data
  and transmit/receive the DMA descriptors.

- This behaviour of auto_restart or free-running mode is fine for
  streaming usecases where display device needs to be provided
  with data at a consistent rate but is not acceptable for mem2mem usecases
  where output needs to have exact 1-to-1 relationship with input
  without any duplication of frames.

- Furthermore this gives a performance benefit for mem2mem usecases
  as the default mode doesn't require to stage a descriptor and
  instead the active descriptor can be marked as complete after
  interrupt is received to process next descriptor.

Signed-off-by: Devarsh Thakkar <devarsh.thakkar@xilinx.com>
Reviewed-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/media/platform/xilinx/xilinx-m2m.c b/drivers/media/platform/xilinx/xilinx-m2m.c
index 0e848a218c7d7d32e9b5021c5a12adfa0a8845e1..097b73937ad17c5da72eb127ebdd21a6d2cc5138 100644 (file)
--- a/drivers/media/platform/xilinx/xilinx-m2m.c
+++ b/drivers/media/platform/xilinx/xilinx-m2m.c
@@ -587,6 +587,7 @@ static void xvip_m2m_prep_submit_dev2mem_desc(struct xvip_m2m_ctx *ctx,
        u32 bpl_nume, bpl_deno;
        u32 luma_size;
        u32 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
+       enum operation_mode mode = DEFAULT;
 
        p_out = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
 
@@ -603,6 +604,7 @@ static void xvip_m2m_prep_submit_dev2mem_desc(struct xvip_m2m_ctx *ctx,
 
        pix_mp = &dma->capfmt.fmt.pix_mp;
        info = dma->capinfo;
+       xilinx_xdma_set_mode(dma->chan_rx, mode);
        xilinx_xdma_v4l2_config(dma->chan_rx, pix_mp->pixelformat);
        xvip_width_padding_factor(pix_mp->pixelformat, &padding_factor_nume,
                                  &padding_factor_deno);
@@ -662,6 +664,7 @@ static void xvip_m2m_prep_submit_mem2dev_desc(struct xvip_m2m_ctx *ctx,
        u32 bpl_nume, bpl_deno;
        u32 luma_size;
        u32 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
+       enum operation_mode mode = DEFAULT;
 
        p_in = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
 
@@ -678,6 +681,7 @@ static void xvip_m2m_prep_submit_mem2dev_desc(struct xvip_m2m_ctx *ctx,
 
        pix_mp = &dma->outfmt.fmt.pix_mp;
        info = dma->outinfo;
+       xilinx_xdma_set_mode(dma->chan_tx, mode);
        xilinx_xdma_v4l2_config(dma->chan_tx, pix_mp->pixelformat);
        xvip_width_padding_factor(pix_mp->pixelformat, &padding_factor_nume,
                                  &padding_factor_deno);