clk/zynq/clkc: Add 'fclk-enable' functionality

In cases no proper drivers are avaiable and enabling the FCLKs through
the CCF and activation through userspace is not an option either, the
clkc needs a way to enable the FCLKs.

A new property - 'fclk-enable' - is added to the DT bindings. It's value
is a bitmask, where a set bit results in enabling the corresponding FCLK
through the clkc.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
(cherry picked from commit d0b69caa6c963ed23f7bd725fcc68670dd2ed257)

diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
index b74de39401098534dea5e4831f98b63a75cab96f..7f686c801a7d43ff1c93d5c515027d691731d675 100644 (file)
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -22,6 +22,8 @@ Required properties:
 Optional properties:
  - clocks : as described in the clock bindings
  - clock-names : as described in the clock bindings
+ - fclk-enable : Bit mask to enable FCLKs in cases no proper CCF compatible
+                driver is available. Bit [0..3] correspond to FCLK0..FCLK3.
 
 Clock inputs:
 The following strings are optional parameters to the 'clock-names' property in

diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 4fc836fc203cae5911f6da7e57945936fcdcbf19..b4f8a51afd57f67cb5793f4963d6f7754cfd29e2 100644 (file)
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -233,6 +233,7 @@ static void __init zynq_clk_setup(struct device_node *np)
        int ret;
        struct clk *clk;
        char *clk_name;
+       unsigned int fclk_enable;
        const char *clk_output_name[clk_max];
        const char *cpu_parents[4];
        const char *periph_parents[4];
@@ -267,6 +268,10 @@ static void __init zynq_clk_setup(struct device_node *np)
        ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,
                        tmp);
 
+       ret = of_property_read_u32(np, "fclk-enable", &fclk_enable);
+       if (ret)
+               fclk_enable = 0;
+
        /* PLLs */
        clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
                        SLCR_PLL_STATUS, 0, &armpll_lock);
@@ -361,11 +366,18 @@ static void __init zynq_clk_setup(struct device_node *np)
        clk_prepare_enable(clks[dci]);
 
        /* Peripheral clocks */
-       for (i = fclk0; i <= fclk3; i++)
+       for (i = fclk0; i <= fclk3; i++) {
                zynq_clk_register_fclk(i, clk_output_name[i],
                                SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
                                periph_parents);
 
+               if (fclk_enable & BIT(i - fclk0)) {
+                       if (clk_prepare_enable(clks[i]))
+                               pr_warn("%s: FCLK%u enable failed\n",
+                                       __func__, i - fclk0);
+               }
+       }
+
        zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
                        SLCR_LQSPI_CLK_CTRL, periph_parents, 0);