return 0;
}
+static int xilinxphy_of_init(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->dev;
+ struct device_node *of_node = dev->of_node;
+ u32 phytype;
+
+ if (!IS_ENABLED(CONFIG_OF_MDIO))
+ return 0;
+
+ if (!of_node)
+ return -ENODEV;
+
+ if (!of_property_read_u32(of_node, "xlnx,phy-type", &phytype))
+ if (phytype == XAE_PHY_TYPE_1000BASE_X)
+ phydev->dev_flags |= XAE_PHY_TYPE_1000BASE_X;
+
+ return 0;
+}
+
static int xilinxphy_config_init(struct phy_device *phydev)
{
int temp;
+ xilinxphy_of_init(phydev);
temp = phy_read(phydev, MII_BMCR);
temp &= XPCSPMA_PHY_CTRL_ISOLATE_DISABLE;
phy_write(phydev, MII_BMCR, temp);