unsigned int gic_irqs, irq_limit, i;
void __iomem *base = gic->dist_base;
u32 cpumask = 1 << smp_processor_id();
- u32 cpu1mask = 2;
cpumask |= cpumask << 8;
cpumask |= cpumask << 16;
- cpu1mask |= cpu1mask << 8;
- cpu1mask |= cpu1mask << 16;
-
#ifndef CONFIG_XILINX_AMP_CPU1_SLAVE
writel(0, base + GIC_DIST_CTRL);
* Set all global interrupts to this CPU only.
*/
for (i = 32; i < gic_irqs; i += 4) {
-
- /* Xilinx AMP, CPU0 is the master of the GIC, but put the 2nd
- set of devices onto CPU1 for now. For CPU1 testing, just
- put all devices onto CPU1.
- */
-
-#if !defined(CONFIG_XILINX_AMP_CPU0_MASTER) && \
- !defined(CONFIG_XILINX_AMP_CPU1_TEST) && \
- !defined(CONFIG_XILINX_CPU1_TEST)
writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
-
-#elif defined(CONFIG_XILINX_CPU1_TEST)
- writel(cpu1mask, base + GIC_DIST_TARGET + i * 4 / 4);
-
-#elif defined(CONFIG_XILINX_AMP_CPU0_MASTER)
- if (i < 68)
- writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
- else
- writel(cpu1mask, base + GIC_DIST_TARGET + i * 4 / 4);
-#endif
}
/*
local_irq_restore(flags);
}
-#if defined(CONFIG_SMP) || defined(CONFIG_XILINX_AMP_CPU0_MASTER)
+#if defined(CONFIG_SMP) || defined(CONFIG_XILINX_AMP_CPU0_MASTER) || defined(CONFIG_XILINX_CPU1_TEST)
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
{
unsigned long map = *cpus_addr(*mask);
gic_init(0, 29, (void __iomem *)SCU_GIC_DIST_BASE, gic_cpu_base_addr);
+ /* when running in AMP mode on CPU0, allocate unused interrupts to the
+ * other CPU so another OS can run on it, or if just running Linux on
+ * the 2nd CPU as a test, do the same
+ */
+#if defined(CONFIG_XILINX_AMP_CPU0_MASTER) || defined(CONFIG_XILINX_CPU1_TEST)
+ printk("Xilinx AMP: Setting IRQs to CPU1\n");
+ gic_set_cpu(1, IRQ_TIMERCOUNTER1);
+ gic_set_cpu(1, IRQ_TIMERCOUNTER1 + 1);
+ gic_set_cpu(1, IRQ_UART1);
+ gic_set_cpu(1, IRQ_I2C1);
+ gic_set_cpu(1, IRQ_ETH1);
+ gic_set_cpu(1, IRQ_SPI1);
+ gic_set_cpu(1, SDIO1_IRQ);
+#endif
+
pr_debug("<-irq_init\n");
}