mtd: m25p80: xilinx: Force 3 byte addressing for zynq qspi for large flash size

Hack the addr width to 3 in case of large size flash connected to
zynq qspi controller and force this only if the connected spi controller
is zynq ps qspi.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 3fbc8371f827c1b8fe4807356cfb40903ca0789f..f7353a55f6f7470fac59f3dc336665d422abfaf4 100644 (file)
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -1182,8 +1182,17 @@ static int m25p_probe(struct spi_device *spi)
        else {
                /* enable 4-byte addressing if the device exceeds 16MiB */
                if (flash->mtd.size > 0x1000000) {
-                       flash->addr_width = 4;
-                       set_4byte(flash, info->jedec_id, 1);
+                       struct device_node *np;
+                       const char *comp_str;
+                       np = of_get_next_parent(spi->dev.of_node);
+                       of_property_read_string(np, "compatible", &comp_str);
+                       if (!strcmp(comp_str, "xlnx,ps7-qspi-1.00.a")) {
+                               flash->addr_width = 3;
+                               set_4byte(flash, info->jedec_id, 0);
+                       } else {
+                               flash->addr_width = 4;
+                               set_4byte(flash, info->jedec_id, 1);
+                       }
                } else
                        flash->addr_width = 3;
        }