spi: xilinx-qps: Added macros for bank instructions and lqspi

Opcode definitions for Bank instructions of Spansion and Micron.
Opcode definition for Flag status register read and added these
opcodes to Instruction format table.

Macro for linear qspi config register upper page bit mask.

Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/spi/spi-xilinx-qps.c b/drivers/spi/spi-xilinx-qps.c
index 4ceabc8d0f510fd02fef54e691e76beeb3a46cd5..061a74118137f9fddc91172570b7ede5f5295cb9 100644 (file)
--- a/drivers/spi/spi-xilinx-qps.c
+++ b/drivers/spi/spi-xilinx-qps.c
@@ -94,6 +94,7 @@
  */
 #define XQSPIPS_LCFG_TWO_MEM_MASK      0x40000000 /* LQSPI Two memories Mask */
 #define XQSPIPS_LCFG_SEP_BUS_MASK      0x20000000 /* LQSPI Separate bus Mask */
+#define XQSPIPS_LCFG_U_PAGE_MASK       0x10000000 /* LQSPI Upper Page Mask */
 
 #define XQSPIPS_LCFG_DUMMY_SHIFT       8
 
@@ -121,9 +122,14 @@
 #define        XQSPIPS_FLASH_OPCODE_WRDS       0x04    /* Write disable */
 #define        XQSPIPS_FLASH_OPCODE_RDSR1      0x05    /* Read status register 1 */
 #define        XQSPIPS_FLASH_OPCODE_WREN       0x06    /* Write enable */
+#define        XQSPIPS_FLASH_OPCODE_BRRD       0x16    /* Bank Register Read */
+#define        XQSPIPS_FLASH_OPCODE_BRWR       0x17    /* Bank Register Write */
+#define        XQSPIPS_FLASH_OPCODE_EXTADRD    0xC8    /* Micron - Bank Reg Read */
+#define        XQSPIPS_FLASH_OPCODE_EXTADWR    0xC5    /* Micron - Bank Reg Write */
 #define        XQSPIPS_FLASH_OPCODE_FAST_READ  0x0B    /* Fast read data bytes */
 #define        XQSPIPS_FLASH_OPCODE_BE_4K      0x20    /* Erase 4KiB block */
 #define        XQSPIPS_FLASH_OPCODE_RDSR2      0x35    /* Read status register 2 */
+#define        XQSPIPS_FLASH_OPCODE_RDFSR      0x70    /* Read flag status register */
 #define        XQSPIPS_FLASH_OPCODE_DUAL_READ  0x3B    /* Dual read data bytes */
 #define        XQSPIPS_FLASH_OPCODE_BE_32K     0x52    /* Erase 32KiB block */
 #define        XQSPIPS_FLASH_OPCODE_QUAD_READ  0x6B    /* Quad read data bytes */
@@ -206,6 +212,7 @@ static struct xqspips_inst_format flash_inst[] = {
        { XQSPIPS_FLASH_OPCODE_RDSR1, 1, XQSPIPS_TXD_00_01_OFFSET },
        { XQSPIPS_FLASH_OPCODE_RDSR2, 1, XQSPIPS_TXD_00_01_OFFSET },
        { XQSPIPS_FLASH_OPCODE_WRSR, 1, XQSPIPS_TXD_00_01_OFFSET },
+       { XQSPIPS_FLASH_OPCODE_RDFSR, 1, XQSPIPS_TXD_00_01_OFFSET },
        { XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_00_OFFSET },
        { XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_00_OFFSET },
        { XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_00_OFFSET },
@@ -218,6 +225,10 @@ static struct xqspips_inst_format flash_inst[] = {
        { XQSPIPS_FLASH_OPCODE_FAST_READ, 1, XQSPIPS_TXD_00_01_OFFSET },
        { XQSPIPS_FLASH_OPCODE_DUAL_READ, 1, XQSPIPS_TXD_00_01_OFFSET },
        { XQSPIPS_FLASH_OPCODE_QUAD_READ, 1, XQSPIPS_TXD_00_01_OFFSET },
+       { XQSPIPS_FLASH_OPCODE_BRRD, 1, XQSPIPS_TXD_00_01_OFFSET },
+       { XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_00_10_OFFSET },
+       { XQSPIPS_FLASH_OPCODE_EXTADRD, 1, XQSPIPS_TXD_00_01_OFFSET },
+       { XQSPIPS_FLASH_OPCODE_EXTADWR, 2, XQSPIPS_TXD_00_10_OFFSET },
        /* Add all the instructions supported by the flash device */
 };