PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node.

Updated Zynq PCI binding documentation with Microblaze node.
Update kernel configuration for AXI PCIe Host Bridge driver to support
Microblaze.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
index 02f979a48aeb2a40f3942f6669b464508c4faafe..55449b687b3445fd52e915823eece2e1cff31663 100644 (file)
--- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -17,7 +17,10 @@ Required properties:
        Please refer to the standard PCI bus binding document for a more
        detailed explanation
 
-Optional properties:
+Optional properties for Zynq:
+- bus-range: PCI bus numbers covered
+
+Required property for Microblaze:
 - bus-range: PCI bus numbers covered
 
 Interrupt controller child node
@@ -38,7 +41,7 @@ the four INTx interrupts in ISR and route them to this domain.
 
 Example:
 ++++++++
-
+Zynq:
        pci_express: axi-pcie@50000000 {
                #address-cells = <3>;
                #size-cells = <2>;
@@ -60,3 +63,30 @@ Example:
                        #interrupt-cells = <1>;
                };
        };
+
+
+Microblaze:
+       pci_express: axi-pcie@10000000 {
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+               compatible = "xlnx,axi-pcie-host-1.00.a";
+               reg = <0x10000000 0x4000000>;
+               device_type = "pci";
+               interrupt-parent = <&microbalze_0_intc>;
+               interrupts = <1 2>;
+               interrupt-map-mask = <0 0 0 7>;
+               interrupt-map = <0 0 0 1 &pcie_intc 1>,
+                               <0 0 0 2 &pcie_intc 2>,
+                               <0 0 0 3 &pcie_intc 3>,
+                               <0 0 0 4 &pcie_intc 4>;
+               ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
+               bus-range = <0x00 0xff>;
+
+               pcie_intc: interrupt-controller {
+                       interrupt-controller;
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+               };
+
+       };