net: ethernet: axienet: Fix comments blocks

There is rule for network drivers with comments blocks
which is newly checked by checkpatch.pl script.
Let's fix it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index fb6da1e6144ce05bacab20100927af83652ebfb6..d27382cd7b03902d2514fac5e0b0c57aaa891587 100644 (file)
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -198,9 +198,7 @@ static int axienet_dma_bd_init(struct net_device *ndev)
        lp->tx_bd_tail = 0;
        lp->rx_bd_ci = 0;
 
-       /*
-        * Allocate the Tx and Rx buffer descriptors.
-        */
+       /* Allocate the Tx and Rx buffer descriptors */
        lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
                                         sizeof(*lp->tx_bd_v) * TX_BD_NUM,
                                         &lp->tx_bd_p,
@@ -275,7 +273,8 @@ static int axienet_dma_bd_init(struct net_device *ndev)
        axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
 
        /* Populate the tail pointer and bring the Rx Axi DMA engine out of
-        * halted state. This will make the Rx side ready for reception.*/
+        * halted state. This will make the Rx side ready for reception.
+        */
        axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
        cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
        axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
@@ -285,7 +284,8 @@ static int axienet_dma_bd_init(struct net_device *ndev)
 
        /* Write to the RS (Run-stop) bit in the Tx channel control register.
         * Tx channel is now ready to run. But only after we write to the
-        * tail pointer register that the Tx channel will start transmitting */
+        * tail pointer register that the Tx channel will start transmitting.
+        */
        axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
        cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
        axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
@@ -366,7 +366,8 @@ static void axienet_set_multicast_list(struct net_device *ndev)
            netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
                /* We must make the kernel realize we had to move into
                 * promiscuous mode. If it was a promiscuous mode request
-                * the flag is already set. If not we set it. */
+                * the flag is already set. If not we set it.
+                */
                ndev->flags |= IFF_PROMISC;
                reg = axienet_ior(lp, XAE_FMI_OFFSET);
                reg |= XAE_FMI_PM_MASK;
@@ -450,7 +451,8 @@ static void __axienet_device_reset(struct axienet_local *lp,
        /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
         * process of Axi DMA takes a while to complete as all pending
         * commands/transfers will be flushed or completed during this
-        * reset process. */
+        * reset process.
+        */
        axienet_dma_out32(lp, offset, XAXIDMA_CR_RESET_MASK);
        timeout = DELAY_OF_ONE_MILLISEC;
        while (axienet_dma_in32(lp, offset) & XAXIDMA_CR_RESET_MASK) {
@@ -512,7 +514,8 @@ static void axienet_device_reset(struct net_device *ndev)
        axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
 
        /* Sync default options with HW but leave receiver and
-        * transmitter disabled.*/
+        * transmitter disabled.
+        */
        axienet_setoptions(ndev, lp->options &
                           ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
        axienet_set_mac_address(ndev, NULL);
@@ -937,7 +940,8 @@ static int axienet_open(struct net_device *ndev)
        /* Disable the MDIO interface till Axi Ethernet Reset is completed.
         * When we do an Axi Ethernet reset, it resets the complete core
         * including the MDIO. If MDIO is not disabled when the reset
-        * process is started, MDIO will be broken afterwards. */
+        * process is started, MDIO will be broken afterwards.
+        */
        axienet_iow(lp, XAE_MDIO_MC_OFFSET,
                    (mdio_mcreg & (~XAE_MDIO_MC_MDIOEN_MASK)));
        axienet_device_reset(ndev);
@@ -1400,7 +1404,8 @@ static void axienet_dma_err_handler(unsigned long data)
        /* Disable the MDIO interface till Axi Ethernet Reset is completed.
         * When we do an Axi Ethernet reset, it resets the complete core
         * including the MDIO. So if MDIO is not disabled when the reset
-        * process is started, MDIO will be broken afterwards. */
+        * process is started, MDIO will be broken afterwards.
+        */
        axienet_iow(lp, XAE_MDIO_MC_OFFSET, (mdio_mcreg &
                    ~XAE_MDIO_MC_MDIOEN_MASK));
 
@@ -1471,7 +1476,8 @@ static void axienet_dma_err_handler(unsigned long data)
        axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
 
        /* Populate the tail pointer and bring the Rx Axi DMA engine out of
-        * halted state. This will make the Rx side ready for reception.*/
+        * halted state. This will make the Rx side ready for reception.
+        */
        axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
        cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
        axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
@@ -1481,7 +1487,8 @@ static void axienet_dma_err_handler(unsigned long data)
 
        /* Write to the RS (Run-stop) bit in the Tx channel control register.
         * Tx channel is now ready to run. But only after we write to the
-        * tail pointer register that the Tx channel will start transmitting */
+        * tail pointer register that the Tx channel will start transmitting
+        */
        axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
        cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
        axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
@@ -1497,7 +1504,8 @@ static void axienet_dma_err_handler(unsigned long data)
        axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
 
        /* Sync default options with HW but leave receiver and
-        * transmitter disabled.*/
+        * transmitter disabled.
+        */
        axienet_setoptions(ndev, lp->options &
                           ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
        axienet_set_mac_address(ndev, NULL);

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
index 7ec9cab15074f5898fe2f43a72866cca767ba152..a53baf9fa24c537f7f92c80691a61f42878a8b2d 100644 (file)
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
@@ -189,7 +189,8 @@ int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np)
                        /* If there is any remainder from the division of
                         * fHOST / (MAX_MDIO_FREQ * 2), then we need to add 1
                         * to the clock divisor or we will surely be
-                        * above 2.5 MHz */
+                        * above 2.5 MHz
+                        */
                        if (host_clock % (MAX_MDIO_FREQ * 2))
                                clk_div++;
                        dev_dbg(lp->dev,