]> rtime.felk.cvut.cz Git - zynq/linux.git/commitdiff
zynqmp: firmware: Adds zynqmp-aes support
authorKalyani Akula <kalyani.akula@xilinx.com>
Fri, 14 Sep 2018 09:12:46 +0000 (14:42 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 7 Nov 2018 10:03:52 +0000 (11:03 +0100)
This patch adds zynqmp_pm_aes_engine support for
AES encryption and decryption from the Linux.

Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/firmware/xilinx/zynqmp/firmware.c
include/linux/firmware/xilinx/zynqmp/firmware.h

index 1abe3e5649623bb20d3275a574d957d8388f710f..6b8f53ddf7f5f2c4d88eeab76deb4e435c5f5c7b 100644 (file)
@@ -678,6 +678,29 @@ static int zynqmp_pm_rsa(const u64 address, const u32 size, const u32 flags)
                                   size, flags, NULL);
 }
 
+/**
+ * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
+ * AES-GCM core.
+ * @address:   Address of the AesParams structure.
+ * @out:       Returned output value
+ *
+ * Return:     Returns status, either success or error code.
+ */
+static int zynqmp_pm_aes_engine(const u64 address, u32 *out)
+{
+       u32 ret_payload[PAYLOAD_ARG_CNT];
+       int ret;
+
+       if (!out)
+               return -EINVAL;
+
+       ret = zynqmp_pm_invoke_fn(PM_SECURE_AES, upper_32_bits(address),
+                                 lower_32_bits(address),
+                                 0, 0, ret_payload);
+       *out = ret_payload[1];
+       return ret;
+}
+
 /**
  * zynqmp_pm_pinctrl_request - Request Pin from firmware
  * @pin:       Pin number to request
@@ -1037,6 +1060,7 @@ static const struct zynqmp_eemi_ops eemi_ops = {
        .clock_setparent = zynqmp_pm_clock_setparent,
        .clock_getparent = zynqmp_pm_clock_getparent,
        .register_access = zynqmp_pm_config_reg_access,
+       .aes = zynqmp_pm_aes_engine,
 };
 
 /**
index 3ee281cc4d5b636f43de5fd4a9a8e9f141e27058..c9ccdbf74bb2b14acfb707201bd390d3b92cfa3b 100644 (file)
@@ -127,6 +127,7 @@ enum pm_api_id {
        PM_CLOCK_SETPARENT,
        PM_CLOCK_GETPARENT,
        PM_FPGA_READ = 46,
+       PM_SECURE_AES,
        /* PM_REGISTER_ACCESS API */
        PM_REGISTER_ACCESS = 52,
 };
@@ -603,6 +604,7 @@ struct zynqmp_eemi_ops {
        int (*clock_getparent)(u32 clock_id, u32 *parent_id);
        int (*register_access)(u32 register_access_id, u32 address,
                               u32 mask, u32 value, u32 *out);
+       int (*aes)(const u64 address, u32 *out);
 };
 
 /*