* @axi_clk: Pointer to the AXI clock
* @axi4_clk: Pointer to the AXI4 clock
* @spi_clk: Pointer to the SPI clock
+ * @dev: Pointer to the device
* @rx_ptr: Pointer to the RX buffer
* @tx_ptr: Pointer to the TX buffer
* @bytes_per_word: Number of bytes in a word
struct clk *axi_clk;
struct clk *axi4_clk;
struct clk *spi_clk;
+ struct device *dev;
u8 *rx_ptr;
const u8 *tx_ptr;
u8 bytes_per_word;
static int xspi_setup(struct spi_device *qspi)
{
int ret;
+ struct xilinx_spi *xqspi = spi_master_get_devdata(qspi->master);
if (qspi->master->busy)
return -EBUSY;
- ret = pm_runtime_get_sync(&qspi->dev);
+ ret = pm_runtime_get_sync(xqspi->dev);
if (ret < 0)
return ret;
ret = xspi_setup_transfer(qspi, NULL);
- pm_runtime_put_sync(&qspi->dev);
+ pm_runtime_put_sync(xqspi->dev);
return ret;
}
static int xspi_prepare_transfer_hardware(struct spi_master *master)
{
struct xilinx_spi *xqspi = spi_master_get_devdata(master);
+
u32 cr;
int ret;
- ret = pm_runtime_get_sync(&master->dev);
+ ret = pm_runtime_get_sync(xqspi->dev);
if (ret < 0)
return ret;
cr &= ~XSPI_CR_ENABLE;
xqspi->write_fn(cr, xqspi->regs + XSPI_CR_OFFSET);
- pm_runtime_put_sync(&master->dev);
+ pm_runtime_put_sync(xqspi->dev);
return 0;
}
if (ret < 0)
goto clk_unprepare_all;
+ xspi->dev = &pdev->dev;
+
xspi->read_fn = xspi_read32;
xspi->write_fn = xspi_write32;
/* Detect endianness on the IP via loop bit in CR register*/