#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
#define XEAMCPS_GEN_PURPOSE_TIMER_LOAD 100 /* timeout value is msecs */
-
-#define XSLCR_EMAC0_CLK_CTRL_OFFSET 0x140 /* EMAC0 Reference Clk Control */
-#define XSLCR_EMAC1_CLK_CTRL_OFFSET 0x144 /* EMAC1 Reference Clk Control */
#define BOARD_TYPE_ZYNQ 0x01
#define BOARD_TYPE_PEEP 0x02
-#define XEMACPS_DFLT_SLCR_DIV0_1000 8
-#define XEMACPS_DFLT_SLCR_DIV1_1000 1
-#define XEMACPS_DFLT_SLCR_DIV0_100 8
-#define XEMACPS_DFLT_SLCR_DIV1_100 5
-#define XEMACPS_DFLT_SLCR_DIV0_10 8
-#define XEMACPS_DFLT_SLCR_DIV1_10 50
-#define XEMACPS_SLCR_DIV_MASK 0xFC0FC0FF
#ifdef CONFIG_XILINX_PS_EMAC_HWTSTAMP
#define NS_PER_SEC 1000000000ULL /* Nanoseconds per