]> rtime.felk.cvut.cz Git - zynq/linux.git/commitdiff
[media] v4l: vsp1: Fix VI6_DPR_ROUTE_FXA_MASK macro
authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Thu, 29 Jan 2015 00:53:55 +0000 (22:53 -0200)
committerMauro Carvalho Chehab <mchehab@osg.samsung.com>
Mon, 6 Jul 2015 11:26:07 +0000 (08:26 -0300)
FXA bit of VI6_DPR_mod_ROUTE register starts from 16bit. But VI6_DPR_ROUTE_FXA_MASK
is set to become start from 8bit. This fixes shift size for VI6_DPR_ROUTE_FXA_MASK.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
drivers/media/platform/vsp1/vsp1_regs.h

index 4177f98968d6a3711ac56bcdf00f1c63ab58b16d..25b48738b1470aa2f40ad3428c821900cbc5d7f6 100644 (file)
 #define VI6_DPR_HST_ROUTE              0x2044
 #define VI6_DPR_HSI_ROUTE              0x2048
 #define VI6_DPR_BRU_ROUTE              0x204c
-#define VI6_DPR_ROUTE_FXA_MASK         (0xff << 8)
+#define VI6_DPR_ROUTE_FXA_MASK         (0xff << 16)
 #define VI6_DPR_ROUTE_FXA_SHIFT                16
 #define VI6_DPR_ROUTE_FP_MASK          (0x3f << 8)
 #define VI6_DPR_ROUTE_FP_SHIFT         8