]> rtime.felk.cvut.cz Git - zynq/linux.git/commitdiff
dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer
authorRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Fri, 15 Jun 2018 14:05:15 +0000 (08:05 -0600)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 19 Jun 2018 08:32:47 +0000 (10:32 +0200)
In AXI CDMA simple mode also pass MSB bits of source and destination
address to xilinx_write function. This fixes simple CDMA operation
mode using 64-bit addressing.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/dma/xilinx/xilinx_dma.c

index 7021a7dd1199d9ce9d224a56abcb47c83d6e90b1..cd307236e7fd0ee51d9a3b10c2436dbecc1ff577 100644 (file)
@@ -1249,8 +1249,10 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
 
                hw = &segment->hw;
 
-               xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw->src_addr);
-               xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw->dest_addr);
+               xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, (dma_addr_t)
+                            ((u64)hw->src_addr_msb << 32 | hw->src_addr));
+               xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, (dma_addr_t)
+                            ((u64)hw->dest_addr_msb << 32 | hw->dest_addr));
 
                /* Start the transfer */
                dma_ctrl_write(chan, XILINX_DMA_REG_BTT,