net: xilinx: Enable emaclite and axi emac for ZynqMP

Use readl/writel for ZynqMP for axi emac.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/net/ethernet/xilinx/Kconfig b/drivers/net/ethernet/xilinx/Kconfig
index 6d68c8a8f4f2ac7f732ff6cfe862c71ae2460a27..27f7f386a83bab72fa231023f86a3f7de3d2abb0 100644 (file)
--- a/drivers/net/ethernet/xilinx/Kconfig
+++ b/drivers/net/ethernet/xilinx/Kconfig
@@ -5,7 +5,7 @@
 config NET_VENDOR_XILINX
        bool "Xilinx devices"
        default y
-       depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS
+       depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS || ARCH_ZYNQMP
        ---help---
          If you have a network (Ethernet) card belonging to this class, say Y.
 
@@ -18,14 +18,14 @@ if NET_VENDOR_XILINX
 
 config XILINX_EMACLITE
        tristate "Xilinx 10/100 Ethernet Lite support"
-       depends on PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS
+       depends on PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS || ARCH_ZYNQMP
        select PHYLIB
        ---help---
          This driver supports the 10/100 Ethernet Lite from Xilinx.
 
 config XILINX_AXI_EMAC
        tristate "Xilinx 10/100/1000 AXI Ethernet support"
-       depends on MICROBLAZE
+       depends on (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
        select PHYLIB
        ---help---
          This driver supports the 10/100/1000 Ethernet from Xilinx for the

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index c337400485dad83ee0fd13a1a32c5dd89ac7b64f..7b477f3066acb1036179c55700396a2b0d465ea2 100644 (file)
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -341,6 +341,16 @@
 
 #define DELAY_OF_ONE_MILLISEC          1000
 
+#define XAXIENET_NAPI_WEIGHT           64
+
+/* Read/Write access to the registers */
+#ifndef out_be32
+#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP)
+#define in_be32(offset)                __raw_readl(offset)
+#define out_be32(offset, val)  __raw_writel(val, offset)
+#endif
+#endif
+
 /**
  * struct axidma_bd - Axi Dma buffer descriptor layout
  * @next:         MM2S/S2MM Next Descriptor Pointer