drm: xlnx: sdi: Fix the VSync_Start and VSync_End for interlaced modes

Fixes the VSync_start and VSync_End for Vertical Sync Line for Field 0
and Field 1 for interlaced modes. The Field 0 is to be incremented by 1
for all interlaced modes. The Field 1 is to be incremented by 2 for 3GB
modes and by 1 for all other interlaced modes.
This can't be fixed in any other way by modifying the timing values in
the modes array.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/gpu/drm/xlnx/xlnx_sdi_timing.c b/drivers/gpu/drm/xlnx/xlnx_sdi_timing.c
index 235415fc22b19302ded20e49dbd46f8045a24487..1769f3f66dfadc0b848e58a9bf4ddfb4cacdbb4a 100644 (file)
--- a/drivers/gpu/drm/xlnx/xlnx_sdi_timing.c
+++ b/drivers/gpu/drm/xlnx/xlnx_sdi_timing.c
@@ -338,8 +338,38 @@ void xlnx_stc_sig(void __iomem *base, struct videomode *vm)
        reg = vsync_start & XSTC_GV1_SYNCSTART_MASK;
        reg |= (vbackporch_start << XSTC_GV1_BPSTART_SHIFT) &
               XSTC_GV1_BPSTART_MASK;
+
+       /*
+        * Fix the Vsync_vstart and vsync_vend of Field 0
+        * for all interlaced modes including 3GB.
+        */
+       if (vm->flags & DISPLAY_FLAGS_INTERLACED)
+               reg = ((((reg & XSTC_GV1_BPSTART_MASK) >>
+                       XSTC_GV1_BPSTART_SHIFT) - 1) <<
+                       XSTC_GV1_BPSTART_SHIFT) |
+                       ((reg & XSTC_GV1_SYNCSTART_MASK) - 1);
+
        xlnx_stc_writel(base, XSTC_GVSYNC_F0, reg);
 
+       /*
+        * Fix the Vsync_vstart and vsync_vend of Field 1
+        * for interlaced and 3GB modes.
+        */
+       if (vm->flags & DISPLAY_FLAGS_INTERLACED) {
+               if (vm->pixelclock == 148500000)
+                       /* Revert and increase by 1 for 3GB mode */
+                       reg = ((((reg & XSTC_GV1_BPSTART_MASK) >>
+                               XSTC_GV1_BPSTART_SHIFT) + 2) <<
+                               XSTC_GV1_BPSTART_SHIFT) |
+                               ((reg & XSTC_GV1_SYNCSTART_MASK) + 2);
+               else
+                       /* Only revert the reduction */
+                       reg = ((((reg & XSTC_GV1_BPSTART_MASK) >>
+                               XSTC_GV1_BPSTART_SHIFT) + 1) <<
+                               XSTC_GV1_BPSTART_SHIFT) |
+                               ((reg & XSTC_GV1_SYNCSTART_MASK) + 1);
+       }
+
        hori_off.v0blank_hori_start = hactive;
        hori_off.v0blank_hori_end = hactive;
        hori_off.v0sync_hori_start = hsync_start;