Xilinx: ARM: BSP: Added early UART clock selection

This is needed to allow the baud rate for the early printk
UART to be setup for EP107 or the newer boards where the
UART input clock is different.

diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 78a8e716e82506fe2a8091efc271137e1a1ac751..836bb6ced599319e278244f7e6233a4e4f4f14f9 100644 (file)
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,13 +1,21 @@
 if ARCH_ZYNQ
 
 menu "Xilinx Specific Options"
-config XILINX_EARLY_UART1
+config ZYNQ_EARLY_UART1
        tristate "Early Printk On UART1 (2nd UART)"
        default n
        help
          Select if you want to use the 2nd UART (UART1) in Zynq for the early
          printk. If not selected, the 1st UART (UART0) is used.
 
+config ZYNQ_EARLY_UART_EP107
+       tristate "Early UART Clock Input For EP107"
+       default y
+       help
+         Select if you want the kernel to be setup for the EP107 board which is
+         using a 50 MHz clock into the UART. Not selecting this causes a clock into
+         the UART that is based on a 33.333 MHz clock divided down by 63.  Note that
+         this only affects early printk.
 
 config XILINX_FIXED_DEVTREE_ADDR
        tristate "Device Tree At Fixed Address"

diff --git a/arch/arm/mach-zynq/include/mach/uart.h b/arch/arm/mach-zynq/include/mach/uart.h
index 033e675ab248cc3ae26894cbfd071327eb38cd53..35a6bf0d999b56b369880fa961db348cce520a07 100644 (file)
--- a/arch/arm/mach-zynq/include/mach/uart.h
+++ b/arch/arm/mach-zynq/include/mach/uart.h
@@ -28,10 +28,16 @@
 #define UART_SR_TXFULL         0x00000010  /* TX FIFO full */
 #define UART_SR_TXEMPTY                0x00000008  /* TX FIFO empty */
 
-#define UART_BAUD_9600         0x145   /* 9600 based on 50 MHz clock */
-#define UART_BAUDDIV_9600      0xF     
-#define UART_BAUD_115K         0x56    /* 115200 based on 50 MHz clock */
-#define UART_BAUDDIV_115K      0x4
+/* The EP107 uses a different clock (50 MHz) right into the UART while the new boards
+   will be using a 33.333 MHz clock into the chip which then is divided by 63.
+*/
+#ifdef CONFIG_XILINX_EARLY_UART_EP107
+       #define UART_BAUD_115K          0x56    /* 115200 based on 50 MHz clock */
+       #define UART_BAUDDIV_115K       0x4
+#else
+       #define UART_BAUD_115K          0x11    /* 115200 based on 33.33MHz / 63 clock */
+       #define UART_BAUDDIV_115K       0x6
+#endif
 
 #ifndef __ASSEMBLY__
 

diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h
index 31e87f43d866484f742cb889e246e6325ad49d43..a2879fbfe6b9aca176c813a69d4eb2b350b89254 100644 (file)
--- a/arch/arm/mach-zynq/include/mach/zynq_soc.h
+++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h
@@ -69,7 +69,8 @@
 #if    defined(CONFIG_XILINX_AMP_CPU1_SLAVE)   || \
        defined(CONFIG_XILINX_CPU1_TEST)        || \
        defined(CONFIG_ZYNQ_AMP_CPU1_SLAVE)     || \
-       defined(CONFIG_ZYNQ_CPU1_TEST)
+       defined(CONFIG_ZYNQ_CPU1_TEST)          || \
+       defined(CONFIG_ZYNQ_EARLY_UART1)
 
        #define LL_UART_PADDR   UART1_PHYS
        #define LL_UART_VADDR   UART1_VIRT