fpga: Align possition of zynqmp in Kconfig

Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm64/configs/xilinx_zynqmp_defconfig b/arch/arm64/configs/xilinx_zynqmp_defconfig
index 9ce833848dd824ad403c2d0c256523fd3f84b432..de8bf293e6a968a54365a5bcfa93bc747a6673e3 100644 (file)
--- a/arch/arm64/configs/xilinx_zynqmp_defconfig
+++ b/arch/arm64/configs/xilinx_zynqmp_defconfig
@@ -346,10 +346,10 @@ CONFIG_ZYNQMP_RESET_CONTROLLER=y
 CONFIG_RAS=y
 CONFIG_NVMEM_ZYNQMP=y
 CONFIG_FPGA=y
-CONFIG_FPGA_MGR_ZYNQMP_FPGA=y
 CONFIG_FPGA_BRIDGE=y
 CONFIG_XILINX_PR_DECOUPLER=y
 CONFIG_FPGA_REGION=y
+CONFIG_FPGA_MGR_ZYNQMP_FPGA=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index f6de4af96393bc1019abbb2673484c0ecbaee1e3..ea2f4673240d07f56b5982c5565f54b6bc9240a0 100644 (file)
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -92,13 +92,6 @@ config FPGA_MGR_ZYNQ_AFI_FPGA
          or designs to work the PS to PL interfaces need to be configured
          like the data bus-width etc.
 
-config FPGA_MGR_ZYNQMP_FPGA
-       tristate "Xilinx Zynqmp FPGA"
-       select XILINX_AFI_FPGA
-       depends on ARCH_ZYNQMP || COMPILE_TEST
-       help
-         FPGA manager driver support for Xilinx ZynqMp FPGAs.
-
 config XILINX_AFI_FPGA
        bool "Xilinx AFI FPGA"
        depends on FPGA_MGR_ZYNQMP_FPGA || COMPILE_TEST
@@ -230,4 +223,13 @@ config FPGA_DFL_PCI
 
          To compile this as a module, choose M here.
 
+config FPGA_MGR_ZYNQMP_FPGA
+       tristate "Xilinx ZynqMP FPGA"
+       depends on ARCH_ZYNQMP || COMPILE_TEST
+       help
+         FPGA manager driver support for Xilinx ZynqMP FPGAs.
+         This driver uses the processor configuration port(PCAP)
+         to configure the programmable logic(PL) through PS
+         on ZynqMP SoC.
+
 endif # FPGA