emmc_reg |= XAE_EMMC_LINKSPD_10;
break;
default:
- dev_err(&ndev->dev, "Speed other than 10, 100 "
- "or 1Gbps is not supported\n");
+ dev_err(&ndev->dev, "Speed other than 10, 100 ");
+ dev_err(&ndev->dev, "or 1Gbps is not supported\n");
break;
}
if (lp->tstamp_config.tx_type ==
HWTSTAMP_TX_ONESTEP_SYNC) {
axienet_create_tsheader(tmp,
- TX_TS_OP_ONESTEP, q);
+ TX_TS_OP_ONESTEP
+ , q);
} else {
axienet_create_tsheader(tmp,
- TX_TS_OP_TWOSTEP, q);
+ TX_TS_OP_TWOSTEP
+ , q);
skb_shinfo(skb)->tx_flags
|= SKBTX_IN_PROGRESS;
cur_p->ptp_tx_skb =
DMA_FROM_DEVICE);
cur_p->cntrl = lp->max_frm_size;
cur_p->status = 0;
- cur_p->sw_id_offset = (phys_addr_t) new_skb;
+ cur_p->sw_id_offset = (phys_addr_t)new_skb;
++q->rx_bd_ci;
q->rx_bd_ci %= RX_BD_NUM;
} else if ((lp->axienet_config->mactype == XAXIENET_1G) ||
(lp->axienet_config->mactype == XAXIENET_2_5G)) {
phydev = of_phy_connect(lp->ndev, lp->phy_node,
- axienet_adjust_link, lp->phy_flags,
+ axienet_adjust_link,
+ lp->phy_flags,
lp->phy_interface);
}
XAXIDMA_BD_CTRL_LENGTH_MASK),
DMA_TO_DEVICE);
if (cur_p->tx_skb)
- dev_kfree_skb_irq((struct sk_buff *) cur_p->tx_skb);
+ dev_kfree_skb_irq((struct sk_buff *)cur_p->tx_skb);
cur_p->phys = 0;
cur_p->cntrl = 0;
cur_p->status = 0;
if (ret < 0)
return ret;
- axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32) val);
+ axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32)val);
axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
(((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
XAE_MDIO_MCR_PHYAD_MASK) |
}
if (!npp) {
dev_warn(lp->dev,
- "Could not find ethernet controller device node.");
+ "Could not find ethernet controller device node.");
dev_warn(lp->dev, "Setting MDIO clock divisor to default %d\n",
- DEFAULT_CLOCK_DIVISOR);
+ DEFAULT_CLOCK_DIVISOR);
clk_div = DEFAULT_CLOCK_DIVISOR;
} else {
if (of_property_read_u32(npp, "clock-frequency", &host_clock)) {
*/
if (host_clock % (MAX_MDIO_FREQ * 2))
clk_div++;
- dev_dbg(lp->dev,
- "Setting MDIO clock divisor to %u "
- "based on %u Hz host clock.\n",
- clk_div, host_clock);
+ dev_dbg(lp->dev, "Setting MDIO clock divisor to %u ",
+ clk_div);
+ dev_dbg(lp->dev, "based on %u Hz host clock.\n",
+ host_clock);
}
of_node_put(npp);
}
of_address_to_resource(npp, 0, &res);
snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
- (unsigned long long) res.start);
+ (unsigned long long)res.start);
bus->priv = lp;
bus->name = "Xilinx Axi Ethernet MDIO";