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(parent: 7b2c496) | patch
misc: xilinx-sdfec: Fix AXIS_ENABLE_MASK value
authorDerek Kiernan <derek.kiernan@xilinx.com>
Tue, 15 May 2018 00:16:54 +0000 (01:16 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 15 May 2018 15:22:33 +0000 (17:22 +0200)
commit795d6145b436c5683ef309e97d894e65d5c60431
tree6aafa83555cd5ecb498194a6b21873cc39819355tree | snapshot
parent7b2c4966919edc9d0c16fc50e045a40fc9768a82commit | diff
misc: xilinx-sdfec: Fix AXIS_ENABLE_MASK value

The AXIS_ENABLE register has 6 bits not 5, change value of AXIS_ENABLE_MASK
from 0x1f to 0x3f.

Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/misc/xilinx_sdfec.c diff | blob | history
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