From 795d6145b436c5683ef309e97d894e65d5c60431 Mon Sep 17 00:00:00 2001 From: Derek Kiernan Date: Tue, 15 May 2018 01:16:54 +0100 Subject: [PATCH] misc: xilinx-sdfec: Fix AXIS_ENABLE_MASK value The AXIS_ENABLE register has 6 bits not 5, change value of AXIS_ENABLE_MASK from 0x1f to 0x3f. Signed-off-by: Derek Kiernan Signed-off-by: Michal Simek --- drivers/misc/xilinx_sdfec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/xilinx_sdfec.c b/drivers/misc/xilinx_sdfec.c index eb09fdea23fc..b28562b754a9 100644 --- a/drivers/misc/xilinx_sdfec.c +++ b/drivers/misc/xilinx_sdfec.c @@ -52,7 +52,7 @@ static dev_t xsdfec_devt; #define XSDFEC_ACTIVE_ADDR (0x00008) #define XSDFEC_AXIS_WIDTH_ADDR (0x0000c) #define XSDFEC_AXIS_ENABLE_ADDR (0x00010) -#define XSDFEC_AXIS_ENABLE_MASK (0x0001F) +#define XSDFEC_AXIS_ENABLE_MASK (0x0003F) #define XSDFEC_FEC_CODE_ADDR (0x00014) #define XSDFEC_ORDER_ADDR (0x00018) -- 2.39.2