1 Xilinx ZynqMp AFI interface Manager
3 The Zynq UltraScale+ MPSoC Processing System core provides access from PL
4 masters to PS internal peripherals, and memory through AXI FIFO interface
8 -compatible: Should contain "xlnx,afi-fpga"
9 -config-afi: Pairs of <regid value >
11 The possible values of regid and values are
12 regid: Regids of the register to be written possible values
29 - value: Array of values to be written.
30 for FM0_RDCTRL(0) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
31 for FM0_WRCTRL(1) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
32 for FM1_RDCTRL(2) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
33 for FM1_WRCTRL(3) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
34 for FM2_RDCTRL(4) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
35 for FM2_WRCTRL(5) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
36 for FM3_RDCTRL(6) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
37 for FM3_WRCTRL(7) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
38 for FM4_RDCTRL(8) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
39 for FM4_WRCTRL(9) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
40 for FM5_RDCTRL(10) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
41 for FM5_WRCTRL(11) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
42 for FM6_RDCTRL(12) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
43 for FM6_WRCTRL(13) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled
45 dw_ss1_sel bits (11:10)
47 0x0: 32-bit AXI data width),
48 0x1: 64-bit AXI data width,
50 All other bits are 0 write ignored.
52 for AFI_FA(15) selects for ss2AXI data width valid values
53 0x000: 32-bit AXI data width),
54 0x100: 64-bit AXI data width,
55 0x200: 128-bit AXI data
59 compatible = "xlnx,afi-fpga";
60 config-afi = <0 2>, <1 1>, <2 1>;